[llvm] b37b184 - [X86] Add truncate cost model tests to min-legal-vector-width.ll for when we're avoiding 512 bit vectors.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 13 21:09:56 PDT 2020
Author: Craig Topper
Date: 2020-04-13T21:09:40-07:00
New Revision: b37b1840eb90168952832746baba53c4f7581151
URL: https://github.com/llvm/llvm-project/commit/b37b1840eb90168952832746baba53c4f7581151
DIFF: https://github.com/llvm/llvm-project/commit/b37b1840eb90168952832746baba53c4f7581151.diff
LOG: [X86] Add truncate cost model tests to min-legal-vector-width.ll for when we're avoiding 512 bit vectors.
Added:
Modified:
llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll b/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
index c7b2a7747ad5..8a4e774a4a8e 100644
--- a/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
+++ b/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
@@ -125,3 +125,31 @@ define void @sext512() "min-legal-vector-width"="512" {
%F = sext <32 x i8> undef to <32 x i16>
ret void
}
+
+define void @trunc256() "min-legal-vector-width"="256" {
+; VEC256-LABEL: 'trunc256'
+; VEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %A = trunc <8 x i64> undef to <8 x i32>
+; VEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %B = trunc <8 x i64> undef to <8 x i16>
+; VEC256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %C = trunc <8 x i64> undef to <8 x i8>
+; VEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %D = trunc <16 x i32> undef to <16 x i16>
+; VEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %E = trunc <16 x i32> undef to <16 x i8>
+; VEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %F = trunc <32 x i16> undef to <32 x i8>
+; VEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; VEC512-LABEL: 'trunc256'
+; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %A = trunc <8 x i64> undef to <8 x i32>
+; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %B = trunc <8 x i64> undef to <8 x i16>
+; VEC512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %C = trunc <8 x i64> undef to <8 x i8>
+; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = trunc <16 x i32> undef to <16 x i16>
+; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = trunc <16 x i32> undef to <16 x i8>
+; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F = trunc <32 x i16> undef to <32 x i8>
+; VEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+ %A = trunc <8 x i64> undef to <8 x i32>
+ %B = trunc <8 x i64> undef to <8 x i16>
+ %C = trunc <8 x i64> undef to <8 x i8>
+ %D = trunc <16 x i32> undef to <16 x i16>
+ %E = trunc <16 x i32> undef to <16 x i8>
+ %F = trunc <32 x i16> undef to <32 x i8>
+ ret void
+}
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