[PATCH] D78069: [llvm][CodeGen] Fix issue for SVE gather prefetch.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
fpetrogalli added reviewers: sdesmalen, andwar.
Herald added subscribers: llvm-commits, hiraditya, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

The intrinsics that handle SVE prefetches with a vector of base
addresses plus a scalar offset need to be remapped to the unscaled
version of the intrinsic that use the base address plus (unscaled)
vector of offsets.

For these reason, a new codegen pattern is now mapping any of the
vector base + scalar offset invocation, with an offset that is not
handled by the immediate of the corresponding SVE instruction, into an
invocation of the intrinsics that lowers to a `prfb` instruction with
scalar base + vector index addressing mode. In this tranlation
process, the original vector of bases becomes the vector of indexes
(with no scaling because we use the byte version of the instruction,
`prfb`), and the original offset becames the base address.

Example of tranformation, where <val> is any value that cannot be mapped
to an immediate supported by the vector base + immediate instruction:

  prfd p0, [z0.s, <val>]

becomes

  mov x0, <val>
  prfb p0, [x0, z0.s, uxtw]

Notice that the final set of addresses that will be prefetched will be
the same in both situations, becasue  1. each address will be computed as
`z0.s[i] + <val>` (values in the vector z0.s are unscaled), and 2. the
input predicate remain the same across the transformation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78069

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll

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