[PATCH] D77905: [SVE] Remove calls to getBitWidth from AArch64
Christopher Tetreault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 13 17:25:11 PDT 2020
ctetreau updated this revision to Diff 257164.
ctetreau added a comment.
rebase
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77905/new/
https://reviews.llvm.org/D77905
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9196,9 +9196,10 @@
/// or upper half of the vector elements.
static bool areExtractShuffleVectors(Value *Op1, Value *Op2) {
auto areTypesHalfed = [](Value *FullV, Value *HalfV) {
- auto *FullVT = cast<VectorType>(FullV->getType());
- auto *HalfVT = cast<VectorType>(HalfV->getType());
- return FullVT->getBitWidth() == 2 * HalfVT->getBitWidth();
+ auto *FullVT = FullV->getType();
+ auto *HalfVT = HalfV->getType();
+ return FullVT->getPrimitiveSizeInBits().getFixedSize() ==
+ 2 * HalfVT->getPrimitiveSizeInBits().getFixedSize();
};
auto extractHalf = [](Value *FullV, Value *HalfV) {
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