[PATCH] D77899: [SVE] Remove calls to getBitWidth from Hexagon

[Christopher Tetreault via Phabricator via llvm-commits]

ctetreau updated this revision to Diff 257159.
ctetreau added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77899/new/

https://reviews.llvm.org/D77899

Files:
  llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp


Index: llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -165,7 +165,7 @@
 
   if (Src->isVectorTy()) {
     VectorType *VecTy = cast<VectorType>(Src);
-    unsigned VecWidth = VecTy->getBitWidth();
+    unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
     if (useHVX() && isTypeForHVX(VecTy)) {
       unsigned RegWidth = getRegisterBitWidth(true);
       assert(RegWidth && "Non-zero vector register width expected");


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