[PATCH] D76212: [X86] Make v32i16/v64i8 legal types without avx512bw. Use custom splitting instead.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.
Herald added a reviewer: ctetreau.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19833
 
-    In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op),
-                     MVT::v16i8, In, DAG.getUNDEF(MVT::v8i8));
-    return DAG.getNode(ExtendInVecOpc, dl, VT, In);
+    return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
   }
----------------
Maybe update LowerVectorIntUnary so we can use it here? We just need to relax the requirement that the src/dst vector element types are equal which doesn't seem to really necessary.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:20186
+      Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::v16i8, Hi);
+      return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
+    }
----------------
LowerVectorIntUnary?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:21639
+                     DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
+                     DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
+}
----------------
Maybe pull out a common LowerVectorIntVSETCC and have Lower256IntVSETCC/Lower512IntVSETCC wrap it with value type assertions?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:22966
 
-    In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op),
-                     MVT::v16i8, In, DAG.getUNDEF(MVT::v8i8));
-    return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, VT, In);
+    return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
   }
----------------
LowerVectorIntUnary?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76212/new/

https://reviews.llvm.org/D76212