[PATCH] D77997: [PowerPC] Reserve the MachineOperand for ppc-early-ret pass

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: jsji, nemanjai, hfinkel, PowerPC, steven.zhang.
ZhangKang added a project: LLVM.
Herald added subscribers: shchenz, wuzish, hiraditya.
ZhangKang added a parent revision: D76042: [PowerPC] Add the Uses of  implicit register for the BCLRn instruction.

The ppc-early-ret pass use the addReg() to add operand to the new instruction.

  106               BuildMI(
  107                   **PI, J, J->getDebugLoc(),
  108                   TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
  109                   .addReg(J->getOperand(0).getReg())
  110                   .copyImplicitOps(*I);

For example:

  BC undef renamable $cr5lt, %bb.4
  BLR implicit $lr, implicit $rm

Above case will be converted to:

  BCLR $cr5lt, implicit $lr, implicit $rm

It;s obvious that the `BCLR $cr5lt, implicit $lr, implicit $rm` should be `BCLR undef renamable $cr5lt, implicit $lr, implicit $rm`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77997

Files:
  llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
  llvm/test/CodeGen/PowerPC/early-ret-verify.mir
  llvm/test/CodeGen/PowerPC/early-ret.mir


Index: llvm/test/CodeGen/PowerPC/early-ret.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/early-ret.mir
+++ llvm/test/CodeGen/PowerPC/early-ret.mir
@@ -65,7 +65,7 @@
   ; CHECK-LABEL: name: testBCLRn
   ; CHECK: bb.0.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f3, killed renamable $f4
-  ; CHECK:   BCLRn $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
+  ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.1.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
   ; CHECK:   BCLR killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
@@ -106,7 +106,7 @@
   ; CHECK-LABEL: name: testBCLR
   ; CHECK: bb.0.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f3, killed renamable $f4
-  ; CHECK:   BCLR $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
+  ; CHECK:   BCLR killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.1.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
   ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
@@ -139,8 +139,8 @@
   ; CHECK: bb.0.entry:
   ; CHECK: renamable $r4 = LI 0
   ; CHECK: renamable $cr0 = CMPLWI killed renamable $r4, 0
-  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm
+  ; CHECK: BCCLR 68, renamable $cr0, implicit $lr, implicit $rm
   ; CHECK: bb.1:
-  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm
+  ; CHECK: BCCLR 68, killed renamable $cr0, implicit $lr, implicit $rm
   ; CHECK: BLR implicit $lr, implicit $rm
 ...
Index: llvm/test/CodeGen/PowerPC/early-ret-verify.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/early-ret-verify.mir
+++ llvm/test/CodeGen/PowerPC/early-ret-verify.mir
@@ -1,5 +1,5 @@
 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -run-pass=ppc-early-ret -o \
-# RUN:   - %s | FileCheck %s
+# RUN:   - %s -verify-machineinstrs | FileCheck %s
 
 ---
 name:            testEarlyRet
@@ -40,7 +40,7 @@
 
   ; CHECK-LABEL: testEarlyRet
   ; CHECK: bb.0.entry:
-  ; CHECK:   BCLR $cr5lt, implicit $lr, implicit $rm
+  ; CHECK:   BCLR undef renamable $cr5lt, implicit $lr, implicit $rm
   ; CHECK: bb.1:
   ; CHECK:   renamable $r3 = IMPLICIT_DEF
   ; CHECK:   renamable $r4 = IMPLICIT_DEF
Index: llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
+++ llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
@@ -93,8 +93,8 @@
               MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
               MI->setDesc(TII->get(PPC::BCCLR));
               MachineInstrBuilder(*ReturnMBB.getParent(), MI)
-                  .addImm(J->getOperand(0).getImm())
-                  .addReg(J->getOperand(1).getReg());
+                  .add(J->getOperand(0))
+                  .add(J->getOperand(1));
               (*PI)->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;
@@ -111,7 +111,7 @@
               MI->setDesc(
                   TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn));
               MachineInstrBuilder(*ReturnMBB.getParent(), MI)
-                  .addReg(J->getOperand(0).getReg());
+                  .add(J->getOperand(0));
               (*PI)->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;


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