[llvm] d1da1b5 - [X86] Cleanup ISD::BRIND handling code in X86DAGToDAGISel::Select. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-04-11T15:01:05-07:00
New Revision: d1da1b53ff810baed7e6b1518d4cc11f878ac278

URL: https://github.com/llvm/llvm-project/commit/d1da1b53ff810baed7e6b1518d4cc11f878ac278
DIFF: https://github.com/llvm/llvm-project/commit/d1da1b53ff810baed7e6b1518d4cc11f878ac278.diff

LOG: [X86] Cleanup ISD::BRIND handling code in X86DAGToDAGISel::Select. NFC

-Drop llvm:: on MVT::i32
-Use getValueType instead of getSimpleValueType for an equality
check just cause its shorter and doesn't matter.
-Don't create a const SDValue & since its cheap to copy.
-Remove explicit case from MVT enum to EVT.
-Add message to assert.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index b42c4f0e1494..ee57806ac35a 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -4520,9 +4520,9 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
       // Converts a 32-bit register to a 64-bit, zero-extended version of
       // it. This is needed because x86-64 can do many things, but jmp %r32
       // ain't one of them.
-      const SDValue &Target = Node->getOperand(1);
-      assert(Target.getSimpleValueType() == llvm::MVT::i32);
-      SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, EVT(MVT::i64));
+      SDValue Target = Node->getOperand(1);
+      assert(Target.getValueType() == MVT::i32 && "Unexpected VT!");
+      SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, MVT::i64);
       SDValue Brind = CurDAG->getNode(ISD::BRIND, dl, MVT::Other,
                                       Node->getOperand(0), ZextTarget);
       ReplaceNode(Node, Brind.getNode());