[PATCH] D77850: [PowerPC] Exploit rldimi for ori with large immediates
Qiu Chaofan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 9 19:36:07 PDT 2020
qiucf created this revision.
qiucf added reviewers: PowerPC, jsji, nemanjai, steven.zhang, shchenz.
Herald added subscribers: llvm-commits, kbarton, hiraditya.
Herald added a project: LLVM.
This patch exploits `rldimi` instruction for patterns like `or %a, 0b000011110000`, which saves number of instructions in some cases, compared with `li-ori-sldi-or`.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D77850
Files:
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/test/CodeGen/PowerPC/ori_imm32.ll
llvm/test/CodeGen/PowerPC/ori_imm64.ll
Index: llvm/test/CodeGen/PowerPC/ori_imm64.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/ori_imm64.ll
+++ llvm/test/CodeGen/PowerPC/ori_imm64.ll
@@ -15,10 +15,8 @@
define i64 @ori_test_2(i64 %a) {
; CHECK-LABEL: ori_test_2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lis 4, 15
-; CHECK-NEXT: ori 4, 4, 65535
-; CHECK-NEXT: sldi 4, 4, 29
-; CHECK-NEXT: or 3, 3, 4
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: rldimi 3, 4, 29, 15
; CHECK-NEXT: blr
entry:
%or = or i64 %a, 562949416550400 ; 0x1ffffe0000000
@@ -28,9 +26,8 @@
define i64 @ori_test_3(i64 %a) {
; CHECK-LABEL: ori_test_3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lis 4, -32768
-; CHECK-NEXT: rldicr 4, 4, 36, 63
-; CHECK-NEXT: or 3, 3, 4
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: rldimi 3, 4, 3, 28
; CHECK-NEXT: blr
entry:
%or = or i64 %a, 68719476728 ; 0xffffffff8
Index: llvm/test/CodeGen/PowerPC/ori_imm32.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/ori_imm32.ll
+++ llvm/test/CodeGen/PowerPC/ori_imm32.ll
@@ -16,9 +16,8 @@
define i64 @ori_test_b(i64 %a) {
; CHECK-LABEL: ori_test_b:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li 4, 1
-; CHECK-NEXT: sldi 4, 4, 32
-; CHECK-NEXT: or 3, 3, 4
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: rldimi 3, 4, 32, 31
; CHECK-NEXT: blr
entry:
%or = or i64 %a, 4294967296
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -351,6 +351,7 @@
bool tryAsSingleRLWINM(SDNode *N);
bool tryAsSingleRLWINM8(SDNode *N);
bool tryAsSingleRLWIMI(SDNode *N);
+ bool tryAsSingleRLDIMI(SDNode *N);
void PeepholePPC64();
void PeepholePPC64ZExt();
@@ -4542,6 +4543,28 @@
return true;
}
+bool PPCDAGToDAGISel::tryAsSingleRLDIMI(SDNode *N) {
+ assert(N->getOpcode() == ISD::OR && "ISD::OR SDNode expected");
+ uint64_t Imm64;
+ unsigned MB, ME;
+
+ // We won't get fewer instructions if the immediate is 32-bit integer.
+ // rldimi requires the immediate to have sequent ones with both sides zero.
+ if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) ||
+ isUInt<32>(Imm64) || !isRunOfOnes64(Imm64, MB, ME))
+ return false;
+
+ unsigned SH = 63 - ME;
+ SDLoc Dl(N);
+ // Use select64Imm for making LI instr instead of directly putting Imm64
+ SDValue Ops[] = {
+ N->getOperand(0),
+ SDValue(selectI64Imm(CurDAG, getI64Imm(-1, Dl).getNode()), 0),
+ getI32Imm(SH, Dl), getI32Imm(MB, Dl)};
+ CurDAG->SelectNodeTo(N, PPC::RLDIMI, MVT::i64, Ops);
+ return true;
+}
+
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
void PPCDAGToDAGISel::Select(SDNode *N) {
@@ -4789,6 +4812,11 @@
}
}
+ // If this is 'or' against an imm with sequent ones and both sides zero,
+ // try to emit rldimi
+ if (tryAsSingleRLDIMI(N))
+ return;
+
// OR with a 32-bit immediate can be handled by ori + oris
// without creating an immediate in a GPR.
uint64_t Imm64 = 0;
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