[PATCH] D77832: Allow single-bit integer types to have signs. A signed one bit integer is either 0 or -1.

[Chris Lattner via Phabricator via llvm-commits]

lattner created this revision.
Herald added subscribers: llvm-commits, frgossen, grosul1, Joonsoo, liufengdb, lucyrfox, mgester, arpith-jacob, nicolasvasilache, antiagainst, shauheen, burmako, jpienaar, rriddle, mehdi_amini.
Herald added a reviewer: rriddle.
Herald added a project: LLVM.
lattner added a reviewer: antiagainst.
rriddle accepted this revision.
rriddle added inline comments.
This revision is now accepted and ready to land.


================
Comment at: mlir/test/IR/attribute.mlir:84
+    // CHECK-SAME: attr_20 = 1 : ui1
+    attr_20 = 1: ui1,
+    // CHECK-SAME: attr_21 = -1 : si1
----------------
nit: 1 : ui1 

to match the output


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77832

Files:
  mlir/lib/IR/AsmPrinter.cpp
  mlir/lib/IR/StandardTypes.cpp
  mlir/test/IR/attribute.mlir
  mlir/test/IR/invalid.mlir


Index: mlir/test/IR/invalid.mlir
===================================================================
--- mlir/test/IR/invalid.mlir
+++ mlir/test/IR/invalid.mlir
@@ -200,14 +200,6 @@
 
 // -----
 
-func @illegaltype(ui1) // expected-error {{cannot have signedness semantics for i1}}
-
-// -----
-
-func @illegaltype(si1) // expected-error {{cannot have signedness semantics for i1}}
-
-// -----
-
 func @malformed_for_percent() {
   affine.for i = 1 to 10 { // expected-error {{expected SSA operand}}
 
Index: mlir/test/IR/attribute.mlir
===================================================================
--- mlir/test/IR/attribute.mlir
+++ mlir/test/IR/attribute.mlir
@@ -79,7 +79,12 @@
     // CHECK-SAME: attr_18 = 9223372036854775807 : si64
     attr_18 = 9223372036854775807 : si64,
     // CHECK-SAME: attr_19 = 18446744073709551615 : ui64
-    attr_19 = 18446744073709551615 : ui64
+    attr_19 = 18446744073709551615 : ui64,
+    // CHECK-SAME: attr_20 = 1 : ui1
+    attr_20 = 1: ui1,
+    // CHECK-SAME: attr_21 = -1 : si1
+    attr_21 = -1: si1
+
   } : () -> ()
 
   return
Index: mlir/lib/IR/StandardTypes.cpp
===================================================================
--- mlir/lib/IR/StandardTypes.cpp
+++ mlir/lib/IR/StandardTypes.cpp
@@ -103,8 +103,6 @@
     return emitError(loc) << "integer bitwidth is limited to "
                           << IntegerType::kMaxWidth << " bits";
   }
-  if (width == 1 && signedness != IntegerType::Signless)
-    return emitOptionalError(loc, "cannot have signedness semantics for i1");
   return success();
 }
 
Index: mlir/lib/IR/AsmPrinter.cpp
===================================================================
--- mlir/lib/IR/AsmPrinter.cpp
+++ mlir/lib/IR/AsmPrinter.cpp
@@ -1291,11 +1291,12 @@
     break;
   case StandardAttributes::Integer: {
     auto intAttr = attr.cast<IntegerAttr>();
-    // Print all signed/signless integer attributes as signed unless i1.
-    bool isSigned =
-        attrType.isIndex() || (!attrType.isUnsignedInteger() &&
-                               attrType.getIntOrFloatBitWidth() != 1);
-    intAttr.getValue().print(os, isSigned);
+    // Only print attributes as unsigned if they are explicitly unsigned or are
+    // signless 1-bit values.  Indexes, signed values, and multi-bit signless
+    // values print as signed.
+    bool isUnsigned =
+        attrType.isUnsignedInteger() || attrType.isSignlessInteger(1);
+    intAttr.getValue().print(os, !isUnsigned);
 
     // IntegerAttr elides the type if I64.
     if (typeElision == AttrTypeElision::May && attrType.isSignlessInteger(64))


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