[PATCH] D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive

[Kuan Hsu Chen (Zakk) via Phabricator via llvm-commits]

khchen added a comment.

In D77030#1971795 <https://reviews.llvm.org/D77030#1971795>, @asb wrote:

> I can see the argument for changing the default of EnableRVCHintInstrs. Might we be better just doing that, and keeping it as "rvc-hints" to avoid adding negative features?


@asb I had tried it but the default enabling feature should put ProcessorModels like D62592 <https://reviews.llvm.org/D62592> said.
so I reference ARM's `FeatureNoNegativeImmediates` (ARM.td <https://github.com/llvm/llvm-project/blob/71ae267d1f4117473eb00d9fd3391733b843ca3c/llvm/lib/Target/ARM/ARM.td#L406>, ARMPredicates <https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMPredicates.td#L163> ) to add negative features.


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