[PATCH] D77804: [DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: arsenm, jonpa, efriedma, spatel, john.brawn, greened, craig.topper.
Herald added subscribers: danielkiss, kerbowa, dmgreen, hiraditya, kristof.beyls, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.

This patch enables us to peek through the shifted value if we don't demand all the bits/elts.

This is another step towards removing SelectionDAG::GetDemandedBits and just using TargetLowering::SimplifyMultipleUseDemandedBits.

There's a number of regressions that I'm still investigating, notably:

  ARM's UXTB matching code
  DAGCombiner::MatchRotate is struggling as it only matches with legal types + operations
  X86 ends up splitting a funnel shift from another shift/lea

There a few cases where we end up with extra register moves which I think we can accept in exchange for the increaed ILP.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77804

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/bswap.ll
  llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/trunc-combine.ll
  llvm/test/CodeGen/ARM/and-load-combine.ll
  llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/ARM/ror.ll
  llvm/test/CodeGen/ARM/uxtb.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
  llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
  llvm/test/CodeGen/X86/ctpop-combine.ll
  llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
  llvm/test/CodeGen/X86/masked_compressstore.ll
  llvm/test/CodeGen/X86/mul128.ll
  llvm/test/CodeGen/X86/shift-mask.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D77804.256296.patch
Type: text/x-patch
Size: 124364 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200409/9e54ec36/attachment-0001.bin>