[llvm] 7b65b1e - [ARM] Fix misched-int-basic-thumb2.mir typo in check to fix issue reported on D77354

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-04-08T15:48:18+01:00
New Revision: 7b65b1ecd118287b73042dde9ddbf3778e133295

URL: https://github.com/llvm/llvm-project/commit/7b65b1ecd118287b73042dde9ddbf3778e133295
DIFF: https://github.com/llvm/llvm-project/commit/7b65b1ecd118287b73042dde9ddbf3778e133295.diff

LOG: [ARM] Fix misched-int-basic-thumb2.mir typo in check to fix issue reported on D77354

Added: 
    

Modified: 
    llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
index 1918e3144ec8..5d481aa57c80 100644
--- a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
+++ b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
@@ -47,7 +47,7 @@
 # CHECK_SWIFT: Latency    : 3
 # CHECK_R52:   Latency    : 4
 #
-# CHECK :      SU(6):   %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg
+# CHECK:       SU(6):   %6:rgpr = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3