[PATCH] D77712: [Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh created this revision.
Pierre-vh added reviewers: dmgreen, samparker, SjoerdMeijer.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.

This patch adds an implementation of PerformVSELECTCombine in the ARM DAG Combiner that transforms `vselect(not(cond), lhs, rhs)` into `vselect(cond, rhs, lhs)`.

- **Isn't this supposed to be done in the (Target-Independent) DAGCombiner instead?**
  - Yes, and I tried to do it with D77201 <https://reviews.llvm.org/D77201>, which caused issues with the X86 (AVX512) target (= it broke unit tests, which I unfortunately only noticed when it was upstream and I had to revert the change). The DAGCombiner doesn't optimize this for our cases as it doesn't allow truncation of the operands, so we have to do it here.
- **Why do it for MVE Integer Ops only?**
  - It's the only target that was changed by this patch. I get the same result (tests all pass) by removing the `if` around the `setTargetDAGCombine`, so let's be cautious and just enable it for this scenario at first.
  - I believe all others cases are already handled by the DAGCombiner, it's just this case that needs special handling.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77712

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-pred-or.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

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