[PATCH] D75344: [PowerPC] Exploit VSX neg, abs and nabs instruction for f32
Qiu Chaofan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 7 23:57:45 PDT 2020
qiucf added a comment.
In D75344#1967991 <https://reviews.llvm.org/D75344#1967991>, @nemanjai wrote:
> What is the status of this? Also, there is no description for the patch.
I added description and removed unnecessary parent revision. So this patch is ready for review now.
================
Comment at: llvm/test/CodeGen/PowerPC/fma.ll:130
+; CHECK-VSX: fmsubs
+; CHECK-VSX: xsnegdp
; CHECK-VSX-NEXT: blr
----------------
steven.zhang wrote:
> qiucf wrote:
> > I know here looks like a regression. But I'm drafting another patch to disable `nmsub` instruction when no `nsz` flag set. So the pattern will be removed from td file and we can get `xsnmsubadp` naturally.
> So, could you please post that patch here as the parent revision of this one, then update the patch, so that, we could have a clear picture.
Oh, that's not related to this regression. I've updated this patch to change pattern priority.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D75344/new/
https://reviews.llvm.org/D75344
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