[llvm] aa26dd9 - CodeGen: Use Register in more places
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 7 12:59:50 PDT 2020
Author: Matt Arsenault
Date: 2020-04-07T15:59:40-04:00
New Revision: aa26dd985848364df01d3f8f0f3eaccfd5ee80dc
URL: https://github.com/llvm/llvm-project/commit/aa26dd985848364df01d3f8f0f3eaccfd5ee80dc
DIFF: https://github.com/llvm/llvm-project/commit/aa26dd985848364df01d3f8f0f3eaccfd5ee80dc.diff
LOG: CodeGen: Use Register in more places
Added:
Modified:
llvm/include/llvm/CodeGen/MachineOperand.h
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.h
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index ac1a4d1b2bc5..0f252137364c 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -612,14 +612,14 @@ class MachineOperand {
/// It is sometimes necessary to detach the register mask pointer from its
/// machine operand. This static method can be used for such detached bit
/// mask pointers.
- static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
+ static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
// See TargetRegisterInfo.h.
assert(PhysReg < (1u << 30) && "Not a physical register");
return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
}
/// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
- bool clobbersPhysReg(unsigned PhysReg) const {
+ bool clobbersPhysReg(MCRegister PhysReg) const {
return clobbersPhysReg(getRegMask(), PhysReg);
}
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index c5a90b0c46e3..35aab5018fa4 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -98,7 +98,7 @@ class MachineRegisterInfo {
/// first member of the pair being non-zero. If the hinted register is
/// virtual, it means the allocator should prefer the physical register
/// allocated to it if any.
- IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
+ IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
VirtReg2IndexFunctor> RegAllocHints;
/// PhysRegUseDefLists - This is an array of the head of the use/def list for
@@ -232,7 +232,7 @@ class MachineRegisterInfo {
/// Disables the register from the list of CSRs.
/// I.e. the register will not appear as part of the CSR mask.
/// \see UpdatedCalleeSavedRegs.
- void disableCalleeSavedRegister(unsigned Reg);
+ void disableCalleeSavedRegister(MCRegister Reg);
/// Returns list of callee saved registers.
/// The function returns the updated CSR list (after taking into account
@@ -748,7 +748,7 @@ class MachineRegisterInfo {
/// temporarily while constructing machine instructions. Most operations are
/// undefined on an incomplete register until one of setRegClass(),
/// setRegBank() or setSize() has been called on it.
- unsigned createIncompleteVirtualRegister(StringRef Name = "");
+ Register createIncompleteVirtualRegister(StringRef Name = "");
/// getNumVirtRegs - Return the number of virtual registers created.
unsigned getNumVirtRegs() const { return VRegInfo.size(); }
@@ -760,7 +760,7 @@ class MachineRegisterInfo {
/// specified virtual register. This is typically used by target, and in case
/// of an earlier hint it will be overwritten.
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
- assert(Register::isVirtualRegister(VReg));
+ assert(VReg.isVirtual());
RegAllocHints[VReg].first = Type;
RegAllocHints[VReg].second.clear();
RegAllocHints[VReg].second.push_back(PrefReg);
@@ -779,8 +779,8 @@ class MachineRegisterInfo {
setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
}
- void clearSimpleHint(unsigned VReg) {
- assert (RegAllocHints[VReg].first == 0 &&
+ void clearSimpleHint(Register VReg) {
+ assert (!RegAllocHints[VReg].first &&
"Expected to clear a non-target hint!");
RegAllocHints[VReg].second.clear();
}
@@ -788,12 +788,12 @@ class MachineRegisterInfo {
/// getRegAllocationHint - Return the register allocation hint for the
/// specified virtual register. If there are many hints, this returns the
/// one with the greatest weight.
- std::pair<unsigned, unsigned>
+ std::pair<Register, Register>
getRegAllocationHint(Register VReg) const {
assert(VReg.isVirtual());
- unsigned BestHint = (RegAllocHints[VReg.id()].second.size() ?
- RegAllocHints[VReg.id()].second[0] : 0);
- return std::pair<unsigned, unsigned>(RegAllocHints[VReg.id()].first,
+ Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
+ RegAllocHints[VReg.id()].second[0] : Register());
+ return std::pair<Register, Register>(RegAllocHints[VReg.id()].first,
BestHint);
}
@@ -801,15 +801,15 @@ class MachineRegisterInfo {
/// a target independent hint.
Register getSimpleHint(Register VReg) const {
assert(VReg.isVirtual());
- std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
- return Hint.first ? 0 : Hint.second;
+ std::pair<Register, Register> Hint = getRegAllocationHint(VReg);
+ return Hint.first ? Register() : Hint.second;
}
/// getRegAllocationHints - Return a reference to the vector of all
/// register allocation hints for VReg.
- const std::pair<unsigned, SmallVector<unsigned, 4>>
- &getRegAllocationHints(unsigned VReg) const {
- assert(Register::isVirtualRegister(VReg));
+ const std::pair<Register, SmallVector<Register, 4>>
+ &getRegAllocationHints(Register VReg) const {
+ assert(VReg.isVirtual());
return RegAllocHints[VReg];
}
@@ -876,7 +876,7 @@ class MachineRegisterInfo {
/// canReserveReg - Returns true if PhysReg can be used as a reserved
/// register. Any register can be reserved before freezeReservedRegs() is
/// called.
- bool canReserveReg(unsigned PhysReg) const {
+ bool canReserveReg(MCRegister PhysReg) const {
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
}
@@ -912,7 +912,7 @@ class MachineRegisterInfo {
/// Allocatable registers may show up in the allocation order of some virtual
/// register, so a register allocator needs to track its liveness and
/// availability.
- bool isAllocatable(unsigned PhysReg) const {
+ bool isAllocatable(MCRegister PhysReg) const {
return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
!isReserved(PhysReg);
}
@@ -943,11 +943,11 @@ class MachineRegisterInfo {
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
/// corresponding live-in physical register.
- unsigned getLiveInPhysReg(Register VReg) const;
+ MCRegister getLiveInPhysReg(Register VReg) const;
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
/// corresponding live-in physical register.
- unsigned getLiveInVirtReg(MCRegister PReg) const;
+ Register getLiveInVirtReg(MCRegister PReg) const;
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
/// into the given entry block.
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 07aaddd47f44..ffbcb2bcf114 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -401,7 +401,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
}
/// Returns true if Reg contains RegUnit.
- bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
+ bool hasRegUnit(MCRegister Reg, unsigned RegUnit) const {
for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
if (*Units == RegUnit)
return true;
@@ -412,7 +412,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// operation, in which case we chain backwards through all such operations
/// to the ultimate source register. If a physical register is encountered,
/// we stop the search.
- virtual unsigned lookThruCopyLike(unsigned SrcReg,
+ virtual Register lookThruCopyLike(Register SrcReg,
const MachineRegisterInfo *MRI) const;
/// Return a null-terminated list of all of the callee-saved registers on
@@ -485,13 +485,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// Returns false if we can't guarantee that Physreg, specified as an IR asm
/// clobber constraint, will be preserved across the statement.
virtual bool isAsmClobberable(const MachineFunction &MF,
- unsigned PhysReg) const {
+ MCRegister PhysReg) const {
return true;
}
/// Returns true if PhysReg is unallocatable and constant throughout the
/// function. Used by MachineRegisterInfo::isConstantPhysReg().
- virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
+ virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
/// Returns true if the register class is considered divergent.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
@@ -503,14 +503,14 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// have call sequences where a GOT register may be updated by the caller
/// prior to a call and is guaranteed to be restored (also by the caller)
/// after the call.
- virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
+ virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
const MachineFunction &MF) const {
return false;
}
/// This is a wrapper around getCallPreservedMask().
/// Return true if the register is preserved after the call.
- virtual bool isCalleeSavedPhysReg(unsigned PhysReg,
+ virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
const MachineFunction &MF) const;
/// Prior to adding the live-out mask to a stackmap or patchpoint
@@ -520,7 +520,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// Return a super-register of the specified register
/// Reg so its sub-register of index SubIdx is Reg.
- unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
+ unsigned getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
const TargetRegisterClass *RC) const {
return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
}
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 270ba125df00..f627f58a7362 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -143,7 +143,7 @@ MachineRegisterInfo::recomputeRegClass(Register Reg) {
return true;
}
-unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
+Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
Register Reg = Register::index2VirtReg(getNumVirtRegs());
VRegInfo.grow(Reg);
RegAllocHints.grow(Reg);
@@ -448,20 +448,20 @@ bool MachineRegisterInfo::isLiveIn(Register Reg) const {
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
/// corresponding live-in physical register.
-unsigned MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
+MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->second == VReg)
return I->first;
- return 0;
+ return MCRegister();
}
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
/// corresponding live-in physical register.
-unsigned MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
+Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->first == PReg)
return I->second;
- return 0;
+ return Register();
}
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
@@ -610,7 +610,7 @@ bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const {
return false;
}
-void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
+void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
assert(Reg && (Reg < TRI->getNumRegs()) &&
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index f45ca102d620..bb240572e82b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -83,7 +83,7 @@ bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
const CCValAssign &ArgLoc = ArgLocs[I];
if (!ArgLoc.isRegLoc())
continue;
- Register Reg = ArgLoc.getLocReg();
+ MCRegister Reg = ArgLoc.getLocReg();
// Only look at callee saved registers.
if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
continue;
@@ -93,7 +93,7 @@ bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
SDValue Value = OutVals[I];
if (Value->getOpcode() != ISD::CopyFromReg)
return false;
- unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
+ MCRegister ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
if (MRI.getLiveInPhysReg(ArgReg) != Reg)
return false;
}
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 34d1f7e611ab..5c6963ec29a2 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -407,10 +407,10 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
- const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
+ const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
MRI.getRegAllocationHints(VirtReg);
- SmallSet<unsigned, 32> HintedRegs;
+ SmallSet<Register, 32> HintedRegs;
// First hint may be a target hint.
bool Skip = (Hints_MRI.first != 0);
for (auto Reg : Hints_MRI.second) {
@@ -420,8 +420,8 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
}
// Target-independent hints are either a physical or a virtual register.
- unsigned Phys = Reg;
- if (VRM && Register::isVirtualRegister(Phys))
+ Register Phys = Reg;
+ if (VRM && Phys.isVirtual())
Phys = VRM->getPhys(Phys);
// Don't add the same reg twice (Hints_MRI may contain multiple virtual
@@ -429,7 +429,7 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
if (!HintedRegs.insert(Phys).second)
continue;
// Check that Phys is a valid hint in VirtReg's register class.
- if (!Register::isPhysicalRegister(Phys))
+ if (!Phys.isPhysical())
continue;
if (MRI.isReserved(Phys))
continue;
@@ -446,7 +446,7 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
}
bool TargetRegisterInfo::isCalleeSavedPhysReg(
- unsigned PhysReg, const MachineFunction &MF) const {
+ MCRegister PhysReg, const MachineFunction &MF) const {
if (PhysReg == 0)
return false;
const uint32_t *callerPreservedRegs =
@@ -511,15 +511,15 @@ unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg,
return getRegSizeInBits(*RC);
}
-unsigned
-TargetRegisterInfo::lookThruCopyLike(unsigned SrcReg,
+Register
+TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
const MachineRegisterInfo *MRI) const {
while (true) {
const MachineInstr *MI = MRI->getVRegDef(SrcReg);
if (!MI->isCopyLike())
return SrcReg;
- unsigned CopySrcReg;
+ Register CopySrcReg;
if (MI->isCopy())
CopySrcReg = MI->getOperand(1).getReg();
else {
@@ -527,7 +527,7 @@ TargetRegisterInfo::lookThruCopyLike(unsigned SrcReg,
CopySrcReg = MI->getOperand(2).getReg();
}
- if (!Register::isVirtualRegister(CopySrcReg))
+ if (!CopySrcReg.isVirtual())
return CopySrcReg;
SrcReg = CopySrcReg;
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 61834874a869..345cbbf0fc8e 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -222,7 +222,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
- unsigned Reg) const {
+ MCRegister Reg) const {
return getReservedRegs(MF)[Reg];
}
@@ -240,11 +240,11 @@ void AArch64RegisterInfo::emitReservedArgRegCallError(
}
bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
- unsigned PhysReg) const {
+ MCRegister PhysReg) const {
return !isReservedReg(MF, PhysReg);
}
-bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
+bool AArch64RegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index 905bfb5f4c0b..4d28ce76e362 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -34,7 +34,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
return getEncodingValue(i);
}
- bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
+ bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
bool isAnyArgRegReserved(const MachineFunction &MF) const;
void emitReservedArgRegCallError(const MachineFunction &MF) const;
@@ -83,8 +83,8 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isAsmClobberable(const MachineFunction &MF,
- unsigned PhysReg) const override;
- bool isConstantPhysReg(unsigned PhysReg) const override;
+ MCRegister PhysReg) const override;
+ bool isConstantPhysReg(MCRegister PhysReg) const override;
const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF,
unsigned Kind = 0) const override;
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 9e057a82a43f..c60e43be3eca 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -220,7 +220,7 @@ getReservedRegs(const MachineFunction &MF) const {
}
bool ARMBaseRegisterInfo::
-isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {
+isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const {
return !getReservedRegs(MF).test(PhysReg);
}
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index ef705be80ce8..f9f50576396c 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -134,7 +134,7 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isAsmClobberable(const MachineFunction &MF,
- unsigned PhysReg) const override;
+ MCRegister PhysReg) const override;
const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF,
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 60153e106e2c..c637fb98da75 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -373,7 +373,7 @@ bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) co
return false;
}
-bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg,
+bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
const MachineFunction &MF) const {
assert(Register::isPhysicalRegister(PhysReg));
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index be131da61ee8..b9d035406587 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -92,7 +92,8 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
- bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
+ bool isCallerPreservedPhysReg(MCRegister PhysReg,
+ const MachineFunction &MF) const override;
/// We require the register scavenger.
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index e8e68852d6bd..05f1b22fd409 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -92,11 +92,11 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
- unsigned PhysReg) const {
+ MCRegister PhysReg) const {
return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
}
-bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
+bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
return PhysReg == RISCV::X0;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 023a4ee2f1e8..23b74657c99e 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -31,9 +31,9 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isAsmClobberable(const MachineFunction &MF,
- unsigned PhysReg) const override;
+ MCRegister PhysReg) const override;
- bool isConstantPhysReg(unsigned PhysReg) const override;
+ bool isConstantPhysReg(MCRegister PhysReg) const override;
const uint32_t *getNoPreservedMask() const override;
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