[PATCH] D77580: [llvm-objdump] Fix incomplete relocation output for -D -r mode

[Jason Liu via Phabricator via llvm-commits]

jasonliu updated this revision to Diff 255735.
jasonliu added a comment.

Add comments for print in the middle behavior.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77580/new/

https://reviews.llvm.org/D77580

Files:
  llvm/test/tools/llvm-objdump/XCOFF/disassemble-all.test
  llvm/tools/llvm-objdump/llvm-objdump.cpp


Index: llvm/tools/llvm-objdump/llvm-objdump.cpp
===================================================================
--- llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1514,18 +1514,12 @@
         outs() << CommentStream.str();
         Comments.clear();
 
-        // If disassembly has failed, continue with the next instruction, to
-        // avoid analysing invalid/incomplete instruction information.
-        if (!Disassembled) {
-          outs() << "\n";
-          Index += Size;
-          continue;
-        }
-
-        // Try to resolve the target of a call, tail call, etc. to a specific
-        // symbol.
-        if (MIA && (MIA->isCall(Inst) || MIA->isUnconditionalBranch(Inst) ||
-                    MIA->isConditionalBranch(Inst))) {
+        // If disassembly has failed, avoid analysing invalid/incomplete
+        // instruction information. Otherwise, try to resolve the target of a
+        // call, tail call, etc. to a specific symbol.
+        if (Disassembled && MIA &&
+            (MIA->isCall(Inst) || MIA->isUnconditionalBranch(Inst) ||
+             MIA->isConditionalBranch(Inst))) {
           uint64_t Target;
           if (MIA->evaluateBranch(Inst, SectionAddr + Index, Size, Target)) {
             // In a relocatable object, the target's section must reside in
@@ -1582,7 +1576,7 @@
 
         // Hexagon does this in pretty printer
         if (Obj->getArch() != Triple::hexagon) {
-          // Print relocation for instruction.
+          // Print relocation for instruction and data.
           while (RelCur != RelEnd) {
             uint64_t Offset = RelCur->getOffset();
             // If this relocation is hidden, skip it.
@@ -1591,7 +1585,11 @@
               continue;
             }
 
-            // Stop when RelCur's offset is past the current instruction.
+            // Stop when RelCur's offset is past the disassembled
+            // instruction/data. Note that it's possible the disassembled data
+            // is not the complete data, and we would see relocation prints in
+            // the middle of the complete data. But this matches the binutils
+            // objdump output.
             if (Offset >= Index + Size)
               break;
 
Index: llvm/test/tools/llvm-objdump/XCOFF/disassemble-all.test
===================================================================
--- llvm/test/tools/llvm-objdump/XCOFF/disassemble-all.test
+++ llvm/test/tools/llvm-objdump/XCOFF/disassemble-all.test
@@ -1,7 +1,7 @@
 # REQUIRES: powerpc-registered-target
 
 # RUN: llvm-objdump -D %p/Inputs/xcoff-section-headers.o | \
-# RUN:   FileCheck --check-prefixes=CHECK,ONLY-D %s
+# RUN:   FileCheck %s
 
 # RUN: llvm-objdump -D -r %p/Inputs/xcoff-section-headers.o | \
 # RUN:   FileCheck --check-prefixes=CHECK,WITH-R %s
@@ -35,18 +35,24 @@
 CHECK:        Disassembly of section .data:
 CHECK:        00000080 <func>:
 CHECK-NEXT:       80: 00 00 00 94                  	<unknown>
+WITH-R-NEXT:                         00000080:  R_POS        func
 CHECK:        00000084 <a>:
 CHECK-NEXT:       84: 00 00 00 a4                  	<unknown>
+WITH-R-NEXT:                         00000084:  R_POS        a
 CHECK:        00000088 <b>:
 CHECK-NEXT:       88: 00 00 00 a0                  	<unknown>
+WITH-R-NEXT:                         00000088:  R_POS        b
 CHECK:        0000008c <c>:
 CHECK-NEXT:       8c: 00 00 00 08                  	<unknown>
+WITH-R-NEXT:                         0000008c:  R_TLS        c
 CHECK:        00000090 <d>:
-ONLY-D-NEXT:      90: 00 00 00 00                  	<unknown>
-WITH-R-NEXT:      ...
+CHECK-NEXT:       90: 00 00 00 00                  	<unknown>
+WITH-R-NEXT:                         00000090:  R_TLS        d
 CHECK:        00000094 <func>:
 CHECK-NEXT:       94: 00 00 00 00                  	<unknown>
+WITH-R-NEXT:                         00000094:  R_POS        .func
 CHECK-NEXT:       98: 00 00 00 80                  	<unknown>
+WITH-R-NEXT:                         00000098:  R_POS        TOC
 CHECK-NEXT:       9c: 00 00 00 00                  	<unknown>
 CHECK:        000000a0 <b>:
 CHECK-NEXT:       a0: 00 00 30 39                  	<unknown>


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