[PATCH] D77646: [PowerPC] Fold vector merges of swapped vectors to merge the opposite half

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, PowerPC.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.
Herald added a project: LLVM.

There are quite a few sequences that will produce a swap followed by a merge (low/high). This is mainly due to the SCALAR_TO_VECTOR on little endian requiring a swap (since all PPC instructions have a big endian bias). Due to its prevalence, these sequences often appear in fairly hot code, so we want to get rid of unnecessary swaps.

This patch does two things:

1. Convert a merge (high/low) to the opposite merge if both inputs are swapped
2. Convert a merge (high/low) to the opposite merge if one input is swapped and the other is symmetrical about the midpoint


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77646

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
  llvm/test/CodeGen/PowerPC/load-and-splat.ll
  llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll
  llvm/test/CodeGen/PowerPC/merge_of_swap.ll
  llvm/test/CodeGen/PowerPC/pr25080.ll
  llvm/test/CodeGen/PowerPC/pr38087.ll
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
  llvm/test/CodeGen/PowerPC/qpx-load-splat.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
  llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
  llvm/test/CodeGen/PowerPC/swaps-le-6.ll
  llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll

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