[llvm] 4fc59a4 - Revert "[CodeGen][SelectionDAG] Flip Booleans More Often"
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 7 01:09:35 PDT 2020
Author: Pierre-vh
Date: 2020-04-07T09:09:10+01:00
New Revision: 4fc59a468ff43e6ea25f5184053f763b9fa34590
URL: https://github.com/llvm/llvm-project/commit/4fc59a468ff43e6ea25f5184053f763b9fa34590
DIFF: https://github.com/llvm/llvm-project/commit/4fc59a468ff43e6ea25f5184053f763b9fa34590.diff
LOG: Revert "[CodeGen][SelectionDAG] Flip Booleans More Often"
This reverts commit 23342bdcc888835e744f38a2fcd0a5c651e33a31.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/Thumb2/mve-pred-or.ll
llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d9b70e88c451..4d23dc9c0573 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2592,27 +2592,23 @@ static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
if (V.getOpcode() != ISD::XOR)
return SDValue();
- ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1),
- /*AllowUndefs*/ false,
- /*AllowTruncation*/ true);
+ ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
if (!Const)
return SDValue();
EVT VT = V.getValueType();
bool IsFlip = false;
- APInt ConstValue =
- Const->getAPIntValue().sextOrTrunc(VT.getScalarSizeInBits());
- switch (TLI.getBooleanContents(VT)) {
- case TargetLowering::ZeroOrOneBooleanContent:
- IsFlip = ConstValue.isOneValue();
- break;
- case TargetLowering::ZeroOrNegativeOneBooleanContent:
- IsFlip = ConstValue.isAllOnesValue();
- break;
- case TargetLowering::UndefinedBooleanContent:
- IsFlip = (ConstValue & 0x01) == 1;
- break;
+ switch(TLI.getBooleanContents(VT)) {
+ case TargetLowering::ZeroOrOneBooleanContent:
+ IsFlip = Const->isOne();
+ break;
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:
+ IsFlip = Const->isAllOnesValue();
+ break;
+ case TargetLowering::UndefinedBooleanContent:
+ IsFlip = (Const->getAPIntValue() & 0x01) == 1;
+ break;
}
if (IsFlip)
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
index 2f39ea66e7eb..26ff81c6f394 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
@@ -6,7 +6,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.i32 ne, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -21,7 +22,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.i32 eq, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -36,7 +38,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 ge, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -51,7 +54,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 le, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -66,7 +70,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 gt, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -81,7 +86,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 lt, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -110,7 +116,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.i32 eq, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -158,7 +165,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i3
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.i32 ne, q1, q2
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -173,7 +181,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i3
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.i32 eq, q1, q2
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -188,7 +197,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 le, q2, q1
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -203,7 +213,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 le, q1, q2
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -218,7 +229,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 lt, q2, q1
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -233,7 +245,8 @@ define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vcmpt.s32 lt, q1, q2
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <4 x i32> %a, zeroinitializer
@@ -327,7 +340,8 @@ define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i16 ne, q0, zr
; CHECK-NEXT: vcmpt.i16 ne, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <8 x i16> %a, zeroinitializer
@@ -342,7 +356,8 @@ define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i16 ne, q0, zr
; CHECK-NEXT: vcmpt.i16 ne, q1, q2
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <8 x i16> %a, zeroinitializer
@@ -358,7 +373,8 @@ define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 ne, q0, zr
; CHECK-NEXT: vcmpt.i8 ne, q1, zr
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <16 x i8> %a, zeroinitializer
@@ -373,7 +389,8 @@ define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 ne, q0, zr
; CHECK-NEXT: vcmpt.i8 ne, q1, q2
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq <16 x i8> %a, zeroinitializer
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
index 28280c4205b8..9e793caac3dd 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
@@ -109,7 +109,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp one <4 x float> %src, %src2
@@ -484,7 +485,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q1, q0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ugt <4 x float> %src, %src2
@@ -536,7 +538,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp uge <4 x float> %src, %src2
@@ -588,7 +591,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ult <4 x float> %src, %src2
@@ -640,7 +644,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ule <4 x float> %src, %src2
@@ -693,7 +698,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ord <4 x float> %src, %src2
@@ -1013,7 +1019,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp one <8 x half> %src, %src2
@@ -1898,7 +1905,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ugt <8 x half> %src, %src2
@@ -2022,7 +2030,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp uge <8 x half> %src, %src2
@@ -2146,7 +2155,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ult <8 x half> %src, %src2
@@ -2270,7 +2280,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ule <8 x half> %src, %src2
@@ -2395,7 +2406,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ord <8 x half> %src, %src2
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
index a049544e21a4..c9325c282893 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
@@ -113,7 +113,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -509,7 +510,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -564,7 +566,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -619,7 +622,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -674,7 +678,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -730,7 +735,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -1054,7 +1060,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half* %src2p,
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -1946,7 +1953,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half* %src2p,
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -2071,7 +2079,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half* %src2p,
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -2196,7 +2205,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half* %src2p,
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -2321,7 +2331,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half* %src2p,
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -2447,7 +2458,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half* %src2p,
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -2698,7 +2710,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %sr
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -3094,7 +3107,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %sr
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -3149,7 +3163,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %sr
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -3204,7 +3219,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %sr
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -3259,7 +3275,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %sr
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -3315,7 +3332,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %sr
; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src2, i32 0
@@ -3639,7 +3657,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half* %src2
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -4531,7 +4550,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half* %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -4656,7 +4676,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half* %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -4781,7 +4802,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half* %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -4906,7 +4928,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half* %src2
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
@@ -5032,7 +5055,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half* %src2
; CHECK-MVEFP-NEXT: ldrh r0, [r0]
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%src2 = load half, half* %src2p
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
index df49417a399c..b6c28c3e1016 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
@@ -109,7 +109,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp one <4 x float> %src, zeroinitializer
@@ -484,7 +485,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ugt <4 x float> %src, zeroinitializer
@@ -536,7 +538,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp uge <4 x float> %src, zeroinitializer
@@ -588,7 +591,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ult <4 x float> %src, zeroinitializer
@@ -640,7 +644,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ule <4 x float> %src, zeroinitializer
@@ -693,7 +698,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ord <4 x float> %src, zeroinitializer
@@ -1005,7 +1011,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp one <8 x half> %src, zeroinitializer
@@ -1862,7 +1869,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ugt <8 x half> %src, zeroinitializer
@@ -1982,7 +1990,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp uge <8 x half> %src, zeroinitializer
@@ -2102,7 +2111,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ult <8 x half> %src, zeroinitializer
@@ -2222,7 +2232,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ule <8 x half> %src, zeroinitializer
@@ -2343,7 +2354,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ord <8 x half> %src, zeroinitializer
@@ -2582,7 +2594,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp one <4 x float> zeroinitializer, %src
@@ -2957,7 +2970,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ugt <4 x float> zeroinitializer, %src
@@ -3009,7 +3023,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp uge <4 x float> zeroinitializer, %src
@@ -3061,7 +3076,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ult <4 x float> zeroinitializer, %src
@@ -3113,7 +3129,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ule <4 x float> zeroinitializer, %src
@@ -3166,7 +3183,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ord <4 x float> zeroinitializer, %src
@@ -3478,7 +3496,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp one <8 x half> zeroinitializer, %src
@@ -4335,7 +4354,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ugt <8 x half> zeroinitializer, %src
@@ -4455,7 +4475,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp uge <8 x half> zeroinitializer, %src
@@ -4575,7 +4596,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ult <8 x half> zeroinitializer, %src
@@ -4695,7 +4717,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ule <8 x half> zeroinitializer, %src
@@ -4816,7 +4839,8 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
-; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: vpnot
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp ord <8 x half> zeroinitializer, %src
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