[PATCH] D76836: [AMDGPU] Add G16 support to image instructions

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

In D76836#1956855 <https://reviews.llvm.org/D76836#1956855>, @Flakebi wrote:

> What is the best way to handle A16 and G16 in instruction selection for GlobalISel?
>
> They are only encoded in the types of arguments and not in the intrinsic id. In legalization, we can simply check the type of derivative and address arguments but afterwards, all arguments are packed into a singe, large value for the non-nsa case or several 32 bit values for nsa.
>  I think it’s hard to detect if this was originally A16 or even only G16 with 32 bit addresses.


I agree that this is sub-optimal, though metadata isn't the right way to go here.

IIRC the current approach is to intuit what the original intent was based on NoReg left over by GlobalISel legalization and the like. However, now that we have G_AMDGPU_xxx MIR opcodes for image instructions after legalization, one option would be to add a magic operand to those machine instructions which encode the A16- and G16-ness.


Repository:
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  https://reviews.llvm.org/D76836/new/

https://reviews.llvm.org/D76836