[llvm] 9e1455d - [ARM] Add ARMv8.6 Fine Grain Traps system registers
Ties Stuij via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 5 06:28:32 PDT 2020
Author: Oliver Stannard
Date: 2020-04-05T14:28:18+01:00
New Revision: 9e1455dc236252a60066c312c6d2e8a7ed66f609
URL: https://github.com/llvm/llvm-project/commit/9e1455dc236252a60066c312c6d2e8a7ed66f609
DIFF: https://github.com/llvm/llvm-project/commit/9e1455dc236252a60066c312c6d2e8a7ed66f609.diff
LOG: [ARM] Add ARMv8.6 Fine Grain Traps system registers
Summary:
This patch upstreams support for the ARMv8.6A Fine Grain Traps (FGT)
extension, which adds 5 new system registers.
See ARMv8.6-FGT in the Arm Architecture Reference Manual Armv8 for more
information.
Reviewers: t.p.northover, rengolin, SjoerdMeijer, ab, momchil.velikov
Reviewed By: SjoerdMeijer
Subscribers: LukeGeeson, ostannard, kristof.beyls, hiraditya, danielkiss, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76991
Added:
llvm/test/MC/AArch64/armv8.6a-fgt.s
llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index bf5e2a106121..2efcf8c68d1e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -373,6 +373,10 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
"true", "Enable BFloat16 Extension" >;
+def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
+ "true", "Enable fine grained virtualization traps extension">;
+
+
//===----------------------------------------------------------------------===//
// Architectures.
//
@@ -403,7 +407,8 @@ def HasV8_5aOps : SubtargetFeature<
def HasV8_6aOps : SubtargetFeature<
"v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
- [HasV8_5aOps, FeatureAMVS, FeatureBF16]>;
+
+ [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps]>;
//===----------------------------------------------------------------------===//
// Register File Description
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 97632041c239..9d42e5431da3 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -148,6 +148,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
// Armv8.6-A Extensions
bool HasBF16 = false;
bool HasAMVS = false;
+ bool HasFineGrainedTraps = false;
// Arm SVE2 extensions
bool HasSVE2AES = false;
@@ -415,6 +416,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
// Armv8.6-A Extensions
bool hasBF16() const { return HasBF16; }
+ bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
bool isLittleEndian() const { return IsLittle; }
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index eac21d7160d7..f1181866c42b 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1502,6 +1502,16 @@ foreach n = 0-15 in {
}
}
+// v8.6a Fine Grained Virtualization Traps
+// Op0 Op1 CRn CRm Op2
+let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {
+def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>;
+def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>;
+def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>;
+def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>;
+def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>;
+}
+
// Cyclone specific system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::ProcAppleA7} }] in
diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s
new file mode 100644
index 000000000000..d5b4f0f2e335
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s
@@ -0,0 +1,35 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+fgt < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
+
+msr HFGRTR_EL2, x0
+msr HFGWTR_EL2, x5
+msr HFGITR_EL2, x10
+msr HDFGRTR_EL2, x15
+msr HDFGWTR_EL2, x20
+// CHECK: msr HFGRTR_EL2, x0 // encoding: [0x80,0x11,0x1c,0xd5]
+// CHECK: msr HFGWTR_EL2, x5 // encoding: [0xa5,0x11,0x1c,0xd5]
+// CHECK: msr HFGITR_EL2, x10 // encoding: [0xca,0x11,0x1c,0xd5]
+// CHECK: msr HDFGRTR_EL2, x15 // encoding: [0x8f,0x31,0x1c,0xd5]
+// CHECK: msr HDFGWTR_EL2, x20 // encoding: [0xb4,0x31,0x1c,0xd5]
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+
+mrs x30, HFGRTR_EL2
+mrs x25, HFGWTR_EL2
+mrs x20, HFGITR_EL2
+mrs x15, HDFGRTR_EL2
+mrs x10, HDFGWTR_EL2
+// CHECK: mrs x30, HFGRTR_EL2 // encoding: [0x9e,0x11,0x3c,0xd5]
+// CHECK: mrs x25, HFGWTR_EL2 // encoding: [0xb9,0x11,0x3c,0xd5]
+// CHECK: mrs x20, HFGITR_EL2 // encoding: [0xd4,0x11,0x3c,0xd5]
+// CHECK: mrs x15, HDFGRTR_EL2 // encoding: [0x8f,0x31,0x3c,0xd5]
+// CHECK: mrs x10, HDFGWTR_EL2 // encoding: [0xaa,0x31,0x3c,0xd5]
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
new file mode 100644
index 000000000000..39c017dbf094
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
@@ -0,0 +1,36 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+fgt -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
+
+[0x80,0x11,0x1c,0xd5]
+[0xa0,0x11,0x1c,0xd5]
+[0xc0,0x11,0x1c,0xd5]
+[0x80,0x31,0x1c,0xd5]
+[0xa0,0x31,0x1c,0xd5]
+
+# CHECK: msr HFGRTR_EL2, x0
+# CHECK: msr HFGWTR_EL2, x0
+# CHECK: msr HFGITR_EL2, x0
+# CHECK: msr HDFGRTR_EL2, x0
+# CHECK: msr HDFGWTR_EL2, x0
+# NOFGT: msr S3_4_C1_C1_4, x0
+# NOFGT: msr S3_4_C1_C1_5, x0
+# NOFGT: msr S3_4_C1_C1_6, x0
+# NOFGT: msr S3_4_C3_C1_4, x0
+# NOFGT: msr S3_4_C3_C1_5, x0
+
+[0x80,0x11,0x3c,0xd5]
+[0xa0,0x11,0x3c,0xd5]
+[0xc0,0x11,0x3c,0xd5]
+[0x80,0x31,0x3c,0xd5]
+[0xa0,0x31,0x3c,0xd5]
+
+# CHECK: mrs x0, HFGRTR_EL2
+# CHECK: mrs x0, HFGWTR_EL2
+# CHECK: mrs x0, HFGITR_EL2
+# CHECK: mrs x0, HDFGRTR_EL2
+# CHECK: mrs x0, HDFGWTR_EL2
+# NOFGT: mrs x0, S3_4_C1_C1_4
+# NOFGT: mrs x0, S3_4_C1_C1_5
+# NOFGT: mrs x0, S3_4_C1_C1_6
+# NOFGT: mrs x0, S3_4_C3_C1_4
+# NOFGT: mrs x0, S3_4_C3_C1_5
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