[PATCH] D77353: [WebAssembly] Add DW_OP_WASM_location_int

[Yury Delendik via Phabricator via llvm-commits]

yurydelendik added a comment.

I'm still curious if something like this will work:

  diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
  index c4dc53337c0..4bbff49606a 100644
  --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
  +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
  @@ -44,2 +44,3 @@ public:
         BaseTypeRef = 8,
  +      WasmLocationArg = 30,
         SignBit = 0x80,
  diff --git a/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp b/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
  index e9463fd53d9..c51039c66ef 100644
  --- a/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
  +++ b/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
  @@ -96,3 +96,3 @@ static DescVector getDescriptions() {
     Descriptions[DW_OP_WASM_location] =
  -      Desc(Op::Dwarf4, Op::SizeLEB, Op::SignedSizeLEB);
  +      Desc(Op::Dwarf4, Op::SizeLEB, Op::WasmLocationArg);
     Descriptions[DW_OP_GNU_push_tls_address] = Desc(Op::Dwarf3);
  @@ -172,2 +172,15 @@ bool DWARFExpression::Operation::extract(DataExtractor Data,
         break;
  +    case Operation::WasmLocationArg:
  +      assert(Operand == 1);
  +      switch (Operands.Op[0]) {
  +        case 0: case 1: case 2:
  +          Operands[Operand] = Data.getULEB128(&Offset);
  +          break;
  +        case 4: // global as uint32
  +          Operands[Operand] = Data.getU32(&Offset);
  +          break;
  +        default:
  +          return false; // Unknown Wasm location
  +      }
  +      break;
       case Operation::SizeBlock:
  @@ -273,2 +286,10 @@ bool DWARFExpression::Operation::print(raw_ostream &OS,
           OS << format(" 0x%02x", Expr->Data.getU8(&Offset));
  +    } else if (Size == Operation::WasmLocationArg) {
  +      assert(Operand == 1);
  +      switch (Operands[0]) {
  +        case 0: case 1: case 2:
  +        case 4: // global as uint32
  +          OS << format(" 0x%" PRIx64, Operands[Operand]);
  +        default: assert(false);
  +      }
       } else {


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D77353