[PATCH] D77018: [MC][RISCV] Make .reloc support arbitrary relocation types
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 2 10:50:10 PDT 2020
luismarques added a comment.
I think this looks good. I'll let @lenary have another look.
================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:93-94
const MCValue &Target) {
+ if (Fixup.getKind() >= FirstLiteralRelocationKind)
+ return true;
switch (Fixup.getTargetKind()) {
----------------
Shouldn't this also check the upper bound?
================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:385-386
+ MCFixupKind Kind = Fixup.getKind();
+ if (Kind >= FirstLiteralRelocationKind)
+ return;
MCContext &Ctx = Asm.getContext();
----------------
Ditto.
================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp:55-56
unsigned Kind = Fixup.getTargetKind();
+ if (Kind >= FirstLiteralRelocationKind)
+ return Kind - FirstLiteralRelocationKind;
if (IsPCRel) {
----------------
Ditto.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77018/new/
https://reviews.llvm.org/D77018
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