[PATCH] D77301: [TargetLowering] Improve expansion of FSHL/FSHR
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 2 05:56:13 PDT 2020
foad marked an inline comment as done.
foad added inline comments.
================
Comment at: llvm/test/CodeGen/X86/fshl.ll:123-124
+; X86-SLOW-NEXT: shrl %eax
+; X86-SLOW-NEXT: andb $31, %cl
+; X86-SLOW-NEXT: xorb $31, %cl
+; X86-SLOW-NEXT: shrl %cl, %eax
----------------
The `andb` is redundant here and in a bunch of other i32/i64 test cases. I would have thought the simplifyDemandedBits machinery could work that out. Any ideas why this isn't already working?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77301/new/
https://reviews.llvm.org/D77301
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