[PATCH] D77250: [GlobalISel][AArch64] Early select stores which have G_IMPLICIT_DEF as the value
Jessica Paquette via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 1 16:21:17 PDT 2020
paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: hiraditya, kristof.beyls, rovka.
These can just be deleted, since they're just stores of undefined values.
This is equivalent to what the DAGCombiner does. It's better to do this later than earlier to make sure we handle any implicit defs introduced during legalization.
https://reviews.llvm.org/D77250
Files:
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -36,6 +36,7 @@
define void @store_8xi16(<8 x i16> %v, <8 x i16>* %ptr) { ret void }
define void @store_16xi8(<16 x i8> %v, <16 x i8>* %ptr) { ret void }
+ define void @imp_def() { ret void }
...
---
@@ -550,3 +551,23 @@
RET_ReallyLR
...
+
+---
+name: imp_def
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ ; Test updater will only ever add one checkline, which will vacuously pass
+ ; since it's just the return. We need to explicitly check that there's no
+ ; store here.
+ ; CHECK-LABEL: name: imp_def
+ ; CHECK-NOT: STR
+ ; CHECK: RET_ReallyLR
+ %0:gpr(p0) = COPY $x0
+ %1:gpr(s64) = G_IMPLICIT_DEF
+ G_STORE %1, %0 :: (store 8)
+ RET_ReallyLR
+
+...
Index: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1728,6 +1728,14 @@
I.setDesc(TII.get(TargetOpcode::COPY));
return true;
}
+ case TargetOpcode::G_STORE: {
+ Register Val = I.getOperand(0).getReg();
+ MachineInstr *ImpDef = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Val, MRI);
+ if (!ImpDef)
+ return false;
+ I.eraseFromParent();
+ return true;
+ }
default:
return false;
}
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