[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

In D71767#1954496 <https://reviews.llvm.org/D71767#1954496>, @paulwalker-arm wrote:

> > What about a scheme where we make the fixed-width vector types proper subregs of the scalable types? That way we can add the fixed-width types to the calling conventions and register classes. Would that be of interest you?
> > 
> > It would be similar to X86's XMM->YMM->ZMM registers (i.e. 128b->256b->512b), except that all of SVE's sub-registers would print the same register name. it's a little hacky, but might polish
>
> The problem here is what fixed-width vector types would you use?  The mapping would be dependent on the target.


I'm not sure if I'm following. If we don't add a vector type to a register class for a target, then it shouldn't be a problem, I think. We should be able to do that programmatically in ISel since we know the max vector width at compile time. E.g. Don't add the 1024b vector types to the ZPR register class for a 512b wide target (or we could create a ZPR and subreg hierarchy instead).

I've posted a back-of-the-envelope patch so we can look at something concrete, D77224 <https://reviews.llvm.org/D77224>. It definitely has some wart, but I think it could be workable going forward.


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