[PATCH] D76773: [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled, fix PR45297

[Kai Luo via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8eb40e41f6ec: [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled (authored by lkail).

Changed prior to commit:
  https://reviews.llvm.org/D76773?vs=253044&id=254077#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76773/new/

https://reviews.llvm.org/D76773

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/pr45297.ll


Index: llvm/test/CodeGen/PowerPC/pr45297.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pr45297.ll
+++ llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -1,11 +1,20 @@
-; RUN: not --crash llc -verify-machineinstrs \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
 ; RUN:   -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
-; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
 
 @Global = dso_local global i32 55, align 4
 
 define dso_local void @test(float %0) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fctiwz f0, f1
+; CHECK-NEXT:    addi r3, r1, -4
+; CHECK-NEXT:    addis r4, r2, Global at toc@ha
+; CHECK-NEXT:    stfiwx f0, 0, r3
+; CHECK-NEXT:    lwz r3, -4(r1)
+; CHECK-NEXT:    stw r3, Global at toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %1 = fptosi float %0 to i32
   store i32 %1, i32* @Global, align 4
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13768,7 +13768,7 @@
         (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
          (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
 
-  if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() ||
+  if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
       cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
     return SDValue();
 


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