[PATCH] D74873: [AMDGPU] Define 16 bit VGPR subregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:18-20
+  list<int> slice =
+    !foldl([]<int>, all, acc, cur,
+           !listconcat(acc, !if(!lt(cur, N), [cur], [])));
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Could use a comment for what this accomplishes 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74873/new/

https://reviews.llvm.org/D74873