[PATCH] D77136: [X86] Do not assume types are legal in getFauxShuffleMask

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope created this revision.
bjope added a reviewer: RKSimon.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

Make sure we do not assert on value types not being
simple in getFauxShuffleMask when analysing operations
such as "v8i16 = truncate v8i24".


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77136

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll


Index: llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+; Verify that we don't crash when compiling this. We used to hit an
+; assert like this
+;
+;   llc: ../include/llvm/CodeGen/ValueTypes.h:251: llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
+;
+; due to getFauxShuffleMask not checking that the VT was simple before a call
+; to getSimpleValueType().
+
+define void @dont_hit_assert(i24 signext %c, i24 signext %d) {
+; CHECK-LABEL: dont_hit_assert:
+; CHECK:       # %bb.0: # %for.cond
+; CHECK-NEXT:    movd %edi, %xmm0
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; CHECK-NEXT:    movdqa {{.*#+}} xmm1 = [16777214,16777213,16777212,16777211]
+; CHECK-NEXT:    paddd %xmm0, %xmm1
+; CHECK-NEXT:    pslld $8, %xmm1
+; CHECK-NEXT:    psrad $8, %xmm1
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    pslld $8, %xmm0
+; CHECK-NEXT:    psrad $8, %xmm0
+; CHECK-NEXT:    movd %esi, %xmm2
+; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
+; CHECK-NEXT:    movdqa %xmm2, %xmm3
+; CHECK-NEXT:    pcmpgtd %xmm0, %xmm3
+; CHECK-NEXT:    pcmpgtd %xmm1, %xmm2
+; CHECK-NEXT:    packssdw %xmm3, %xmm2
+; CHECK-NEXT:    packsswb %xmm0, %xmm2
+; CHECK-NEXT:    pmovmskb %xmm2, %eax
+; CHECK-NEXT:    cmpb $-1, %al
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %for.cond
+; CHECK-NEXT:    shll $8, %edi
+; CHECK-NEXT:    addl $-2560, %edi # imm = 0xF600
+; CHECK-NEXT:    sarl $8, %edi
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    jge .LBB0_2
+; CHECK-NEXT:  # %bb.3: # %for.cond.9
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_2: # %if.then.i
+for.cond:
+  %0 = insertelement <8 x i24> undef, i24 %c, i32 0
+  %1 = shufflevector <8 x i24> %0, <8 x i24> undef, <8 x i32> zeroinitializer
+  %2 = add <8 x i24> %1, <i24 -2, i24 -3, i24 -4, i24 -5, i24 -6, i24 -7, i24 -8, i24 -9>
+  %3 = insertelement <8 x i24> undef, i24 %d, i32 0
+  %4 = shufflevector <8 x i24> %3, <8 x i24> undef, <8 x i32> zeroinitializer
+  %5 = icmp slt <8 x i24> %2, %4
+  %6 = add i24 %c, -10
+  %7 = icmp slt i24 %6, %d
+  %rdx.shuf = shufflevector <8 x i1> %5, <8 x i1> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
+  %bin.rdx = and <8 x i1> %5, %rdx.shuf
+  %rdx.shuf22 = shufflevector <8 x i1> %bin.rdx, <8 x i1> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %bin.rdx23 = and <8 x i1> %bin.rdx, %rdx.shuf22
+  %rdx.shuf24 = shufflevector <8 x i1> %bin.rdx23, <8 x i1> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %bin.rdx25 = and <8 x i1> %bin.rdx23, %rdx.shuf24
+  %8 = extractelement <8 x i1> %bin.rdx25, i32 0
+  %9 = and i1 %8, %7
+  br i1 %9, label %for.cond.9, label %if.then.i
+
+if.then.i:
+  unreachable
+
+for.cond.9:
+  ret void
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7522,6 +7522,9 @@
   case ISD::TRUNCATE:
   case X86ISD::VTRUNC: {
     SDValue Src = N.getOperand(0);
+    // Truncated source must be a simple vector.
+    if (!Src.getValueType().isSimple())
+      return false;
     MVT SrcVT = Src.getSimpleValueType();
     unsigned NumSrcElts = SrcVT.getVectorNumElements();
     unsigned NumBitsPerSrcElt = SrcVT.getScalarSizeInBits();


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