[PATCH] D55380: [AMDGPU] Shrink scalar AND, OR, XOR instructions

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:215-218
+/// Attempt to shink AND/OR/XOR operations requiring non-inlineable literals.
+/// For AND or OR, try using S_BITSET{0,1} to clear or set bits.
+/// If the inverse of the immediate is legal, use ANDN2, ORN2 or
+/// XNOR (as a ^ b == ~(a ^ ~b)).
----------------
Is it worth trying to do the converse too:
ANDN2 -> AND
ORN2 -> OR
XNOR -> XOR
Or would those cases never appear in the first place?


================
Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:231-232
+
+  if (SrcImm->isImm() &&
+      !AMDGPU::isInlinableLiteral32(SrcImm->getImm(), ST.hasInv2PiInlineImm())) {
+    uint32_t Imm = static_cast<uint32_t>(SrcImm->getImm());
----------------
Return early if `!SrcImm->isImm() || AMDGPU::isInlinableLiteral32(SrcImm->getImm(), ST.hasInv2PiInlineImm())`.


================
Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:261-262
+
+    if ((Opc == AMDGPU::S_ANDN2_B32 || Opc == AMDGPU::S_ORN2_B32) &&
+        SrcImm == Src0) {
+      if (!TII->commuteInstruction(MI, false, 1, 2))
----------------
What does this do? I can't see how `SrcImm == Src0` would ever be true here.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55380/new/

https://reviews.llvm.org/D55380