[PATCH] D77121: [Alignment][NFC] Transitionning more getMachineMemOperand call sites

[Guillaume Chatelet via Phabricator via llvm-commits]

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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:994
       bool IsInvariant = false;
-      unsigned Alignment = 0;
+      Align Alignment;
       AAMDNodes AAInfo;
----------------
This is a potential functional change, so I'll mention what I checked for posterity:
There are three instantiations of this class. In all cases, `Alignment` is never read before being written to.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:994
       bool IsInvariant = false;
-      unsigned Alignment = 0;
+      Align Alignment;
       AAMDNodes AAInfo;
----------------
courbet wrote:
> This is a potential functional change, so I'll mention what I checked for posterity:
> There are three instantiations of this class. In all cases, `Alignment` is never read before being written to.
Yes I checked as well manually (by reading the code) and by running all tests and asserting when Alignment was read and equal to zero.


This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77121

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
  llvm/lib/Target/Mips/MipsCallLowering.cpp
  llvm/lib/Target/Mips/MipsFastISel.cpp
  llvm/lib/Target/Mips/MipsInstrInfo.cpp
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/PowerPC/PPCFastISel.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/TableGen/address-space-patfrags.td
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp

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