[llvm] 2a07221 - [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 30 23:22:31 PDT 2020
Author: Craig Topper
Date: 2020-03-30T23:21:58-07:00
New Revision: 2a07221cf3029f2b55503e1c3847699eb6090ad6
URL: https://github.com/llvm/llvm-project/commit/2a07221cf3029f2b55503e1c3847699eb6090ad6
DIFF: https://github.com/llvm/llvm-project/commit/2a07221cf3029f2b55503e1c3847699eb6090ad6.diff
LOG: [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.
Differential Revision: https://reviews.llvm.org/D77092
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c20e40e0c978..3bfc8545e544 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4550,6 +4550,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
unsigned OpOpcode = Operand.getNode()->getOpcode();
switch (Opcode) {
+ case ISD::FREEZE:
+ assert(VT == Operand.getValueType() && "Unexpected VT!");
+ break;
case ISD::TokenFactor:
case ISD::MERGE_VALUES:
case ISD::CONCAT_VECTORS:
More information about the llvm-commits
mailing list