[PATCH] D74316: AMDGPU/GlobalISel: Start selecting image intrinsics

Sebastian Neubauer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 30 02:40:31 PDT 2020


Flakebi added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll:77-79
+; GFX9-NEXT:    s_lshl_b32 s12, s0, 16
+; GFX9-NEXT:    v_and_or_b32 v0, v0, v3, v1
+; GFX9-NEXT:    v_and_or_b32 v1, v2, v3, s12
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It looks like the code should produce correct results but why is s0/s12 put into the undefined part?


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll:2-4
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
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Is gfx9 missing here on purpose?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74316/new/

https://reviews.llvm.org/D74316





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