[PATCH] D64193: [PowerPC] Add exception constraint to FP rounding operations

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:352
+  if (Subtarget.hasVSX()) {
+    setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
+  }
----------------
Why we have this lines of changes here ?


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Comment at: llvm/test/CodeGen/PowerPC/build-vector-tests.ll:1514
 ; P9BE-NEXT:    lfs f2, 4(r3)
+; P9BE-NEXT:    xsrsp f0, f0
 ; P9BE-NEXT:    xxmrghd vs1, vs2, vs1
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Could you please explain more about this extra instruction produced ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64193/new/

https://reviews.llvm.org/D64193