[PATCH] D77034: [PowerPC] Don't do the folding if the operand is R0/X0

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: shchenz, nemanjai, jsji, PowerPC.
Herald added subscribers: wuzish, kbarton, hiraditya.
Herald added a project: LLVM.

We have this transformation in PowerPC peephole:

  Replace instruction:
    renamable $x28 = ADDI8 renamable $x7, -8
    renamable $x28 = ADD8 killed renamable $x28, renamable $x0
    STFD killed renamable $f0, -8, killed renamable $x28 :: (store 8 into %ir._ind_cast99.epil)
  with:
    renamable $x28 = ADDI8 renamable $x7, -16
    STFDX killed renamable $f0, $x0, killed $x28 :: (store 8 into %ir._ind_cast99.epil)

It is invalid as the '$x0' in STFDX is constant 0, not register r0.

  stfdx FRS,RA,RB
  if RA = 0 then b <- 0
  else b <- (RA)
  EA <- b +tea (RB)
  MEM(EA, 8) <- (FRS)
  MEMtag(EA, 8) <- 0


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77034

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir


Index: llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir
+++ llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir
@@ -152,3 +152,16 @@
     ; CHECK: $x6 = LD 4, killed $x4
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+name: testR0
+# Give up the folding if the register is R0/X0
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $f1, $x0, $x3
+    $x4 = ADDI8 killed $x3, -8
+    $x4 = ADD8 killed $x4, $x0
+    STFD killed $f1, -8, killed $x4
+    ; CHECK-NOT: STFDX
+    BLR8 implicit $lr8, implicit $rm
+...
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2597,6 +2597,13 @@
         return true;
     return false;
   };
+
+  // We are trying to replace the ImmOpNo with ScaleReg. Give up if it is
+  // treated as special zero when ScaleReg is R0/X0 register.
+  if (III.ZeroIsSpecialOrig == III.ImmOpNo &&
+      (ScaleReg == PPC::R0 || ScaleReg == PPC::X0))
+    return false;
+
   // Make sure no other def for ToBeChangedReg and ScaleReg between ADD Instr
   // and Imm Instr.
   if (NewDefFor(ToBeChangedReg, *ADDMI, MI) || NewDefFor(ScaleReg, *ADDMI, MI))


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