[PATCH] D77029: Fix out-of-bounds BitVector access in RegScavenger

[Brad Moody via Phabricator via llvm-commits]

bmoody created this revision.
bmoody added a reviewer: MatzeB.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

RegScavenger::determineKillsAndDefs was calling BitVector::clear() which
sets the size of the BitVector to 0. Changed to reset() which un-sets the
contents of the vector but doesn't change the size.

-

This code started tripping an assert after a change I'm working on in BitVector.
I haven't included a test because I have no idea how to exercise this code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77029

Files:
  llvm/lib/CodeGen/RegisterScavenging.cpp


Index: llvm/lib/CodeGen/RegisterScavenging.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterScavenging.cpp
+++ llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -119,7 +119,7 @@
   DefRegUnits.reset();
   for (const MachineOperand &MO : MI.operands()) {
     if (MO.isRegMask()) {
-      TmpRegUnits.clear();
+      TmpRegUnits.reset();
       for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
         for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
           if (MO.clobbersPhysReg(*RURI)) {


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