[PATCH] D76925: [Alignment][NFC] MachineMemOperand::getAlign/getBaseAlign

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet created this revision.
gchatelet added a reviewer: courbet.
Herald added subscribers: llvm-commits, kerbowa, jfb, atanasyan, jrtc27, kbarton, aheejin, hiraditya, jgravelle-google, sbc100, nhaehnle, jvesely, nemanjai, sdardis, dschuff, arsenm.
Herald added a project: LLVM.

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76925

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/CodeGen/MachineMemOperand.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
  llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
  llvm/lib/CodeGen/MachineFunction.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
  llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp
  llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
  llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstructionSelector.cpp

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