[PATCH] D76778: [DAGCombine] Fix splitting indexed loads in ForwardStoreValueToDirectLoad()

Fri Mar 27 05:24:15 PDT 2020

nemanjai marked an inline comment as done.
nemanjai added inline comments.

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Comment at: llvm/test/CodeGen/PowerPC/pr45301.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64-- -verify-machineinstrs < %s | FileCheck %s
+%struct.e.0.1.2.3.12.29 = type { [10 x i32] }
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amyk wrote:
> Add the options like `-ppc-asm-full-reg-names`, `-ppc-vsr-nums-as-vr` to the test case.
The first one, yes. The second one, no because there are no vector registers used.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76778/new/

https://reviews.llvm.org/D76778