[PATCH] D76909: [MachineScheduler] Update available queue on the first mop of a new cycle
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 27 02:06:16 PDT 2020
dmgreen created this revision.
dmgreen added reviewers: atrick, MatzeB, fhahn, arsenm, jsji, steven.zhang.
Herald added subscribers: javed.absar, kbarton, hiraditya, wdng, nemanjai.
dmgreen marked an inline comment as done.
dmgreen added inline comments.
Herald added a subscriber: wuzish.
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Comment at: llvm/test/CodeGen/AArch64/misched-fusion-aes.ll:82
; CHECK: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
-; CHECK-NEXT: aesmc [[VA]], [[VA]]
+; CHECK: aesmc [[VA]], [[VA]]
; CHECK: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
----------------
This one I do know about. The A53 schedule holds the load pipelines for 3 resource cycles, so now decides to push one of the loads down later to not hazard with the other loads. This is similar to the aes_load_store case below I believe.
If a resource can be held for multiple cycles in the schedule model, then an instruction can be placed into the available queue, another instruction can be scheduled, but the first will not be take back out if the two instructions hazard. To fix this, make sure that we update the Available queue even on the first MOp of a cycle, pushing available instructions back into the ready queue if they now conflict.
This happens with some downstream schedules we have around MVE instruction scheduling where we use ResourceCycles=[2] to show the instruction executing over two beats. I'm not sure about the test changes here, but this improves scheduling decisions on our in-order cpu's.
https://reviews.llvm.org/D76909
Files:
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
llvm/test/CodeGen/PowerPC/inc-of-add.ll
llvm/test/CodeGen/PowerPC/ppc32-skip-regs.ll
llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
llvm/test/CodeGen/PowerPC/spe.ll
llvm/test/CodeGen/PowerPC/sub-of-not.ll
llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
llvm/test/CodeGen/PowerPC/vec_splat.ll
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