[PATCH] D76773: [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled, fix PR45297
Kai Luo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 22:48:38 PDT 2020
lkail updated this revision to Diff 253044.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D76773/new/
https://reviews.llvm.org/D76773
Files:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/pr45297.ll
Index: llvm/test/CodeGen/PowerPC/pr45297.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pr45297.ll
+++ llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -1,11 +1,20 @@
-; RUN: not --crash llc -verify-machineinstrs \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
-; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
@Global = dso_local global i32 55, align 4
define dso_local void @test(float %0) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fctiwz 0, 1
+; CHECK-NEXT: addi 3, 1, -4
+; CHECK-NEXT: addis 4, 2, Global at toc@ha
+; CHECK-NEXT: stfiwx 0, 0, 3
+; CHECK-NEXT: lwz 3, -4(1)
+; CHECK-NEXT: stw 3, Global at toc@l(4)
+; CHECK-NEXT: blr
entry:
%1 = fptosi float %0 to i32
store i32 %1, i32* @Global, align 4
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13768,7 +13768,7 @@
(Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
(Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
- if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() ||
+ if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
return SDValue();
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