[PATCH] D76884: [AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:715
+            ReturnAddressSpill[0].VGPR)
+        .addReg(AMDGPU::SGPR30)
+        .addImm(ReturnAddressSpill[0].Lane)
----------------
Avoid hardcoding by checking SIRegisterInfo::getReturnAddressReg?


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1038
 
+static void allocateCFISave(MachineFunction &MF, int &FI, unsigned Reg) {
+  SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
----------------
Register


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1315
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    const DebugLoc &DL, unsigned SGPR,
+    ArrayRef<SIMachineFunctionInfo::SpilledReg> VGPRSpills) const {
----------------
Register


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1353
+    OSBlock << uint8_t(dwarf::DW_OP_bit_piece);
+    // FIXME:
+    const unsigned SGPRBitSize = 32;
----------------
FIXME what?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76884/new/

https://reviews.llvm.org/D76884