[PATCH] D76773: [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled, fix PR45297
Sean Fertile via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 14:08:59 PDT 2020
sfertile added a comment.
A couple minor suggestions. If you agree with them, feel free to land them as an NFC update to the test before commiting this patch.
================
Comment at: llvm/test/CodeGen/PowerPC/pr45297.ll:3
; RUN: -mattr=+altivec -mattr=-power8-vector -mattr=-vsx < %s | FileCheck %s
-; XFAIL: *
----------------
Pre-commiting the test to show the intended change in behaviour is a really good idea. I think it would be more effective if we check for the error we are tying to fix though:
```
; RUN: not --crash llc -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: t{{[0-9]+}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
```
================
Comment at: llvm/test/CodeGen/PowerPC/pr45297.ll:8
%1 = fptosi float %0 to i32
store i32 %1, i32* undef, align 4
ret void
----------------
Nit: can we store to something other then undef? Maybe changing the IR to:
```
@Global = dso_local global i32 55, align 4
define dso_local void @test(float %0) local_unnamed_addr {
entry:
%1 = fptosi float %0 to i32
store i32 %1, i32* @Global, align 4
ret void
}
```
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D76773/new/
https://reviews.llvm.org/D76773
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