[llvm] 7a89a5d - [InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors
Jonathan Roelofs via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 11:10:02 PDT 2020
Author: Jonathan Roelofs
Date: 2020-03-26T12:09:36-06:00
New Revision: 7a89a5d81bbdc0ab6dbd14d9af4a52e64c868423
URL: https://github.com/llvm/llvm-project/commit/7a89a5d81bbdc0ab6dbd14d9af4a52e64c868423
DIFF: https://github.com/llvm/llvm-project/commit/7a89a5d81bbdc0ab6dbd14d9af4a52e64c868423.diff
LOG: [InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors
Fixes https://bugs.llvm.org/show_bug.cgi?id=43665
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
llvm/test/Transforms/InstCombine/vector-xor.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 06ec02789750..d07fc857eedf 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -3069,8 +3069,12 @@ Instruction *InstCombiner::visitXor(BinaryOperator &I) {
// ~(C >>s Y) --> ~C >>u Y (when inverting the replicated sign bits)
Constant *C;
if (match(NotVal, m_AShr(m_Constant(C), m_Value(Y))) &&
- match(C, m_Negative()))
- return BinaryOperator::CreateLShr(ConstantExpr::getNot(C), Y);
+ match(C, m_Negative())) {
+ Constant *NewC = ConstantExpr::getNot(C);
+ if (C->getType()->isVectorTy())
+ NewC = getSafeVectorConstantForBinop(Instruction::LShr, NewC, false);
+ return BinaryOperator::CreateLShr(NewC, Y);
+ }
// ~(C >>u Y) --> ~C >>s Y (when inverting the replicated sign bits)
if (match(NotVal, m_LShr(m_Constant(C), m_Value(Y))) &&
diff --git a/llvm/test/Transforms/InstCombine/vector-xor.ll b/llvm/test/Transforms/InstCombine/vector-xor.ll
index c10e56a6561a..52e904902b51 100644
--- a/llvm/test/Transforms/InstCombine/vector-xor.ll
+++ b/llvm/test/Transforms/InstCombine/vector-xor.ll
@@ -140,7 +140,7 @@ define <4 x i32> @test_v4i32_not_ashr_negative_const(<4 x i32> %a0) {
define <4 x i32> @test_v4i32_not_ashr_negative_const_undef(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_not_ashr_negative_const_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> <i32 2, i32 4, i32 undef, i32 8>, [[A0:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> <i32 2, i32 4, i32 0, i32 8>, [[A0:%.*]]
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
;
%1 = ashr <4 x i32> <i32 -3, i32 -5, i32 undef, i32 -9>, %a0
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