[PATCH] D76356: [AMDGPU] Introduce more scratch registers in the ABI.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D76356#1944135 <https://reviews.llvm.org/D76356#1944135>, @cdevadas wrote:

> In D76356#1942097 <https://reviews.llvm.org/D76356#1942097>, @rampitec wrote:
>
> > Then probably interleave 4 is not a best choice. We may also need to adjust cost of tuples to make aligned allocation more likely.
>
>
> A cost for VGPR registers has been handled with https://reviews.llvm.org/D76417.  This will ensure a balanced allocation of scratch registers & CSRs at every split (once the current patch is in the upstream).


D76417 <https://reviews.llvm.org/D76417> changes the cost of VGPRs, I am speaking about tuples. Assume you interleave by 4. Not you can allocate something into v[64:68] or v[65:69]. If you use the latter you will have a spill of 4 registers around any call site where it is alive. If you use the former you have a chance not to spill it.


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