[PATCH] D76861: [AMDGPU] Fix getEUsPerCU for gfx10 in CU mode

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: arsenm, rampitec, nhaehnle, dstuttard, tpr.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

"Per CU" is a bit simplistic for gfx10, but I couldn't think of a better
name.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76861

Files:
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp


Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -268,6 +268,13 @@
 }
 
 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
+  // "Per CU" really means "per whatever functional block the waves of a
+  // workgroup must share". For gfx10 in CU mode this is the CU, which contains
+  // two SIMDs.
+  if (isGFX10(*STI) && STI->getFeatureBits().test(FeatureCuMode))
+    return 2;
+  // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
+  // two CUs, so a total of four SIMDs.
   return 4;
 }
 


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