[PATCH] D76662: [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32
Justin Hibbits via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 09:13:03 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rG459e8e94886f: [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32 (authored by jhibbits).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D76662/new/
https://reviews.llvm.org/D76662
Files:
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/tls.ll
Index: llvm/test/CodeGen/PowerPC/tls.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/tls.ll
+++ llvm/test/CodeGen/PowerPC/tls.ll
@@ -11,11 +11,11 @@
;OPT1-LABEL: localexec:
define i32 @localexec() nounwind {
entry:
-;OPT0: addis [[REG1:[0-9]+]], 13, a at tprel@ha
-;OPT0-NEXT: addi [[REG2:[0-9]+]], [[REG1]], a at tprel@l
+;OPT0: addis [[REG1:[1-9][0-9]*]], 13, a at tprel@ha
+;OPT0-NEXT: addi [[REG2:[1-9][0-9]*]], [[REG1]], a at tprel@l
;OPT0-NEXT: li [[REG3:[0-9]+]], 42
;OPT0: stw [[REG3]], 0([[REG2]])
-;OPT1: addis [[REG1:[0-9]+]], 13, a at tprel@ha
+;OPT1: addis [[REG1:[1-9][0-9]*]], 13, a at tprel@ha
;OPT1-NEXT: li [[REG3:[0-9]+]], 42
;OPT1: stw [[REG3]], a at tprel@l([[REG1]])
store i32 42, i32* @a, align 4
@@ -36,19 +36,19 @@
}
; OPT1-LABEL: main2:
-; OPT1: addis [[REG1:[0-9]+]], 2, a2 at got@tprel at ha
+; OPT1: addis [[REG1:[1-9][0-9]*]], 2, a2 at got@tprel at ha
; OPT1: ld [[REG2:[0-9]+]], a2 at got@tprel at l([[REG1]])
; OPT1: add {{[0-9]+}}, [[REG2]], a2 at tls
;OPT0-PPC32-LABEL: main2:
-;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_ at l
+;OPT0-PPC32: li [[REG1:[1-9][0-9]*]], _GLOBAL_OFFSET_TABLE_ at l
;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_ at ha
-;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2 at got@tprel([[REG1]])
+;OPT0-PPC32: lwz [[REG2:[1-9][0-9]*]], a2 at got@tprel([[REG1]])
;OPT0-PPC32: add 3, [[REG2]], a2 at tls
;OPT0-PPC32-PIC-LABEL: main2:
;OPT0-PPC32-PIC: .long _GLOBAL_OFFSET_TABLE_-{{.*}}
;OPT0-PPC32-PIC-NOT: li {{[0-9]+}}, _GLOBAL_OFFSET_TABLE_ at l
-;OPT0-PPC32-PIC-NOT: addis {{[0-9]+}}, {{[0-9+]}}, _GLOBAL_OFFSET_TABLE_ at ha
+;OPT0-PPC32-PIC-NOT: addis {{[0-9]+}}, {{[1-9][0-9*]}}, _GLOBAL_OFFSET_TABLE_ at ha
;OPT0-PPC32-PIC-NOT: bl __tls_get_addr(a2 at tlsgd)@PLT
-;OPT0-PPC32-PIC: lwz {{[0-9]+}}, a2 at got@tprel({{[0-9]+}})
+;OPT0-PPC32-PIC: lwz {{[0-9]+}}, a2 at got@tprel({{[1-9][0-9]*}})
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3213,7 +3213,7 @@
def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
[]>, NoEncode<"$rT">;
-def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
+def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
"#LDgotTprelL32",
[(set i32:$rD,
(PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1127,7 +1127,7 @@
(PPCaddisGotTprelHA i64:$reg,
tglobaltlsaddr:$disp))]>,
isPPC64;
-def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
+def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
"#LDgotTprelL",
[(set i64:$rD,
(PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
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