[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension
Alex Bradbury via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 08:39:00 PDT 2020
asb added a comment.
Submitting the comments I have so far - need to continue going through in more detail.
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Comment at: llvm/lib/Target/RISCV/RISCV.td:123
+ "'B' (Bit Manipulation Instructions)",
+ [FeatureExtZbb,
+ FeatureExtZbc,
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Nit: indentation of this list seems arbitrary. I'd have that `[` should be aligned with the first `"` on the line above?
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:1
+//===-- RISCVInstrFormatsB.td - RISCV B Instruction Formats --*- tablegen -*-=//
+//
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Doesn't match the filename
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:9
+//
+// This file describes the RISC-V B extension instruction formats.
+//
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This should probably say something like "This file describes the RISC-V instructions from the standard 'B' Bitmanip extension, version 0.92. This extension has not yet been ratified (meaning LLVM support is experimental)."
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:48
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr>
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You're using a different style here than elsewhere in the backend, where we try to use the basic RISC-V formats as the superclass wherever possible (and where necessary, defining a subclass in RISCVInstrInfo*.td). RVBUnary for instance just seems to be an R-type instruction (albeit, one where the rs2 field is hard coded). Also, for the base instr format class we don't set hasSideEffects/mayLoad/mayStore (these are semantic details that aren't necessarily implied by the isntr format).
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:51
+ : RVInst<(outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1", [], InstFormatI> {
+ bits<5> rs1;
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Should be InstFormatR?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D65649/new/
https://reviews.llvm.org/D65649
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