[PATCH] D76767: [RISCV] Support negative constants in CompressInstEmitter

[Simon Cook via Phabricator via llvm-commits]

simoncook updated this revision to Diff 252826.
simoncook added a comment.

Actually solve the underlying problem.

Contrary to my original description, it is not TableGen that stores immediates as unsigned values, but the OpData structure. We are implicitly casting all immediates from signed to unsigned values. By correcting the type and removing that implicit cast, no explicit cast is needed later on.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76767/new/

https://reviews.llvm.org/D76767

Files:
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp


Index: llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -85,7 +85,7 @@
     MapKind Kind;
     union {
       unsigned Operand; // Operand number mapped to.
-      uint64_t Imm;     // Integer immediate value.
+      int64_t Imm;      // Integer immediate value.
       Record *Reg;      // Physical register.
     } Data;
     int TiedOpIdx = -1; // Tied operand index within the instruction.


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