[PATCH] D76800: [InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors

[Jonathan Roelofs via Phabricator via llvm-commits]

jroelofs created this revision.
jroelofs added reviewers: nlopes, lebedev.ri.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
jroelofs retitled this revision from "[Instcombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors" to "[InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors".

Fixes https://bugs.llvm.org/show_bug.cgi?id=43665


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76800

Files:
  llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
  llvm/test/Transforms/InstCombine/vector-xor.ll


Index: llvm/test/Transforms/InstCombine/vector-xor.ll
===================================================================
--- llvm/test/Transforms/InstCombine/vector-xor.ll
+++ llvm/test/Transforms/InstCombine/vector-xor.ll
@@ -140,8 +140,9 @@
 
 define <4 x i32> @test_v4i32_not_ashr_negative_const_undef(<4 x i32> %a0) {
 ; CHECK-LABEL: @test_v4i32_not_ashr_negative_const_undef(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> <i32 2, i32 4, i32 undef, i32 8>, [[A0:%.*]]
-; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> <i32 -3, i32 -5, i32 undef, i32 -9>, [[A0:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], <i32 -1, i32 -1, i32 -1, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %1 = ashr <4 x i32> <i32 -3, i32 -5, i32 undef, i32 -9>, %a0
   %2 = xor  <4 x i32> <i32 -1, i32 -1, i32 -1, i32 undef>, %1
Index: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -3069,7 +3069,8 @@
     // ~(C >>s Y) --> ~C >>u Y (when inverting the replicated sign bits)
     Constant *C;
     if (match(NotVal, m_AShr(m_Constant(C), m_Value(Y))) &&
-        match(C, m_Negative()))
+        match(C, m_Negative()) &&
+        (!C->getType()->isVectorTy() || !C->containsUndefElement()))
       return BinaryOperator::CreateLShr(ConstantExpr::getNot(C), Y);
 
     // ~(C >>u Y) --> ~C >>s Y (when inverting the replicated sign bits)


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