[llvm] bd069ad - [ARM] Move ConstantIsland and LowOverheadLoops Passes.
Yvan Roux via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 25 08:49:53 PDT 2020
Author: Yvan Roux
Date: 2020-03-25T16:49:21+01:00
New Revision: bd069ad39c9ce174db8a7e0c6a43a9de2d679327
URL: https://github.com/llvm/llvm-project/commit/bd069ad39c9ce174db8a7e0c6a43a9de2d679327
DIFF: https://github.com/llvm/llvm-project/commit/bd069ad39c9ce174db8a7e0c6a43a9de2d679327.diff
LOG: [ARM] Move ConstantIsland and LowOverheadLoops Passes.
Move ARM ConstantIsland and LowOverheadLopps passes later in the pipeline
such that they will be run after the upcoming Machine Outlining pass.
Differential Revision: https://reviews.llvm.org/D76065
Added:
Modified:
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/test/CodeGen/ARM/O3-pipeline.ll
llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
llvm/test/DebugInfo/MIR/ARM/larger-subregister.mir
llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir
llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 63aa65267ef2..947bbc3ad3ee 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -362,6 +362,7 @@ class ARMPassConfig : public TargetPassConfig {
void addPreRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
+ void addPreEmitPass2() override;
std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
};
@@ -541,7 +542,9 @@ void ARMPassConfig::addPreEmitPass() {
// Don't optimize barriers at -O0.
if (getOptLevel() != CodeGenOpt::None)
addPass(createARMOptimizeBarriersPass());
+}
+void ARMPassConfig::addPreEmitPass2() {
addPass(createARMConstantIslandPass());
addPass(createARMLowOverheadLoopsPass());
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index 44fcf2a756b3..6c1a1b22f7f1 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -161,15 +161,15 @@
; CHECK-NEXT: Thumb2 instruction size reduce pass
; CHECK-NEXT: Unpack machine instruction bundles
; CHECK-NEXT: optimise barriers pass
+; CHECK-NEXT: Contiguously Lay Out Funclets
+; CHECK-NEXT: StackMap Liveness Analysis
+; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: ARM constant island placement and branch shortening pass
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: ReachingDefAnalysis
; CHECK-NEXT: ARM Low Overhead Loops pass
-; CHECK-NEXT: Contiguously Lay Out Funclets
-; CHECK-NEXT: StackMap Liveness Analysis
-; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: ARM Assembly Printer
diff --git a/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir b/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
index ab8154edf8c1..ea68187e32a0 100644
--- a/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
+++ b/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
@@ -139,6 +139,7 @@
---
name: _ZN1BC2Ev
alignment: 2
+tracksRegLiveness: true
liveins:
- { reg: '$r0' }
frameInfo:
@@ -154,6 +155,8 @@ stack:
callee-saved-register: '$r4' }
body: |
bb.0.entry:
+ liveins: $r0, $r4, $lr
+
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
@@ -175,6 +178,7 @@ body: |
---
name: _ZN1BC1Ev
alignment: 2
+tracksRegLiveness: true
liveins:
- { reg: '$r0' }
frameInfo:
@@ -190,6 +194,8 @@ stack:
callee-saved-register: '$r4' }
body: |
bb.0.entry:
+ liveins: $r0, $r4, $lr
+
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
diff --git a/llvm/test/DebugInfo/MIR/ARM/larger-subregister.mir b/llvm/test/DebugInfo/MIR/ARM/larger-subregister.mir
index 6fb944e8c97c..a9d1dd44192f 100644
--- a/llvm/test/DebugInfo/MIR/ARM/larger-subregister.mir
+++ b/llvm/test/DebugInfo/MIR/ARM/larger-subregister.mir
@@ -29,8 +29,11 @@
!13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14)
!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "CGRect", scope: !5, file: !3, line: 46, size: 128, elements: !4, runtimeLang: DW_LANG_Swift, identifier: "$sSo6CGRectVD")
name: 'f'
+tracksRegLiveness: true
body: |
bb.0:
+ liveins: $r6
+
DBG_VALUE $s31, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !10
DBG_VALUE $q8, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !10
renamable $r0 = t2ADDri $r6, 144, 14, $noreg, $noreg, debug-location !10
diff --git a/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir b/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir
index 99511280f223..83b5a6f394dc 100644
--- a/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir
+++ b/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir
@@ -67,9 +67,11 @@
...
---
name: fn1
-tracksRegLiveness: false
+tracksRegLiveness: true
body: |
bb.0.entry:
+ liveins: $r0, $r1, $r4, $lr
+
$sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
$r4 = MOVr $r0, 14, $noreg, $noreg
DBG_VALUE $r1, $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !18
diff --git a/llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir b/llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir
index fe1660d7f231..1fa172b97645 100644
--- a/llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir
+++ b/llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir
@@ -39,8 +39,12 @@
!9 = !DILocalVariable(name: "q9", scope: !5, file: !4, line: 1, type: !7)
!20 = !DILocation(line: 0, scope: !5)
name: f
+tracksRegLiveness: true
body: |
bb.2.for.body:
+ liveins: $r2
+
+ t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2.for.body, 0, killed $cpsr, debug-location !20
DBG_VALUE $q8, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 0, 64), debug-location !20
DBG_VALUE $q9, $noreg, !9, !DIExpression(DW_OP_LLVM_fragment, 0, 56), debug-location !20
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