[PATCH] D76778: [DAGCombine] Fix splitting indexed loads in ForwardStoreValueToDirectLoad()

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: niravd, rengolin, PowerPC, nathanchance.
Herald added subscribers: arphaman, hiraditya.
Herald added a project: LLVM.

In `DAGCombiner::visitLOAD()` we perform some checks before breaking up an indexed load. However, we don't do the same checking in `ForwardStoreValueToDirectLoad()` which can lead to failures later during combining (see: https://bugs.llvm.org/show_bug.cgi?id=45301).

This patch just adds the same checks to this function as well.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45301


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76778

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/PowerPC/pr45301.ll


Index: llvm/test/CodeGen/PowerPC/pr45301.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr45301.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64-- -verify-machineinstrs < %s | FileCheck %s
+%struct.e.0.1.2.3.12.29 = type { [10 x i32] }
+
+define dso_local void @g(%struct.e.0.1.2.3.12.29* %agg.result) local_unnamed_addr #0 {
+; CHECK-LABEL: g:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -112(1)
+; CHECK-NEXT:    bl i
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addis 4, 2, g at toc@ha
+; CHECK-NEXT:    addi 4, 4, g at toc@l
+; CHECK-NEXT:    ld 5, 0(4)
+; CHECK-NEXT:    std 5, 0(3)
+; CHECK-NEXT:    ld 5, 16(4)
+; CHECK-NEXT:    std 5, 16(3)
+; CHECK-NEXT:    ld 6, 8(4)
+; CHECK-NEXT:    std 6, 8(3)
+; CHECK-NEXT:    ld 6, 24(4)
+; CHECK-NEXT:    std 6, 24(3)
+; CHECK-NEXT:    lwz 6, 0(3)
+; CHECK-NEXT:    ld 4, 32(4)
+; CHECK-NEXT:    std 4, 32(3)
+; CHECK-NEXT:    li 4, 20
+; CHECK-NEXT:    stwbrx 6, 0, 3
+; CHECK-NEXT:    stwbrx 5, 3, 4
+; CHECK-NEXT:    addi 1, 1, 112
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+entry:
+  %call = tail call signext i32 bitcast (i32 (...)* @i to i32 ()*)()
+  %conv = sext i32 %call to i64
+  %0 = inttoptr i64 %conv to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 dereferenceable(40) %0, i8* nonnull align 4 dereferenceable(40) bitcast (void (%struct.e.0.1.2.3.12.29*)* @g to i8*), i64 40, i1 false)
+  %1 = inttoptr i64 %conv to i32*
+  %2 = load i32, i32* %1, align 4
+  %rev.i = tail call i32 @llvm.bswap.i32(i32 %2)
+  store i32 %rev.i, i32* %1, align 4
+  %incdec.ptr.i.4 = getelementptr inbounds i32, i32* %1, i64 5
+  %3 = load i32, i32* %incdec.ptr.i.4, align 4
+  %rev.i.5 = tail call i32 @llvm.bswap.i32(i32 %3)
+  store i32 %rev.i.5, i32* %incdec.ptr.i.4, align 4
+  ret void
+}
+
+declare i32 @i(...) local_unnamed_addr
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) #1
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare i32 @llvm.bswap.i32(i32)
+
+attributes #0 = { nounwind }
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14481,11 +14481,13 @@
 
   auto ReplaceLd = [&](LoadSDNode *LD, SDValue Val, SDValue Chain) -> SDValue {
     if (LD->isIndexed()) {
-      bool IsSub = (LD->getAddressingMode() == ISD::PRE_DEC ||
-                    LD->getAddressingMode() == ISD::POST_DEC);
-      unsigned Opc = IsSub ? ISD::SUB : ISD::ADD;
-      SDValue Idx = DAG.getNode(Opc, SDLoc(LD), LD->getOperand(1).getValueType(),
-                             LD->getOperand(1), LD->getOperand(2));
+      // Cannot handle opaque target constants and we must respect the user's
+      // request not to split indexes from loads.
+      bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
+                       cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
+      if (HasOTCInc || !MaySplitLoadIndex)
+        return SDValue();
+      SDValue Idx = SplitIndexingFromLoad(LD);
       SDValue Ops[] = {Val, Idx, Chain};
       return CombineTo(LD, Ops, 3);
     }


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